1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/avx2-rr1-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2019 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/raddstoreexpminusmax.h>
15
16
xnn_f32_raddstoreexpminusmax_ukernel__avx2_rr1_p5_x72(size_t elements,const float * input,const float * max,float * output,float * sum,const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])17 void xnn_f32_raddstoreexpminusmax_ukernel__avx2_rr1_p5_x72(
18 size_t elements,
19 const float* input,
20 const float* max,
21 float* output,
22 float* sum,
23 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)])
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const __m256 vi_max = _mm256_broadcast_ss(max);
28 const __m256 vlog2e = _mm256_load_ps(params->avx2_rr1_p5.log2e);
29 const __m256 vmagic_bias = _mm256_load_ps(params->avx2_rr1_p5.magic_bias);
30 const __m256 vminus_ln2 = _mm256_load_ps(params->avx2_rr1_p5.minus_ln2);
31 const __m256 vc5 = _mm256_load_ps(params->avx2_rr1_p5.c5);
32 const __m256 vc4 = _mm256_load_ps(params->avx2_rr1_p5.c4);
33 const __m256 vc3 = _mm256_load_ps(params->avx2_rr1_p5.c3);
34 const __m256 vc2 = _mm256_load_ps(params->avx2_rr1_p5.c2);
35 const __m256 vc1 = _mm256_load_ps(params->avx2_rr1_p5.c1);
36 const __m256 vdenorm_cutoff = _mm256_load_ps(params->avx2_rr1_p5.denorm_cutoff);
37
38 __m256 vacc0 = _mm256_setzero_ps();
39 for (; elements >= 72 * sizeof(float); elements -= 72 * sizeof(float)) {
40 const __m256 vi0 = _mm256_loadu_ps(input);
41 const __m256 vi1 = _mm256_loadu_ps(input + 8);
42 const __m256 vi2 = _mm256_loadu_ps(input + 16);
43 const __m256 vi3 = _mm256_loadu_ps(input + 24);
44 const __m256 vi4 = _mm256_loadu_ps(input + 32);
45 const __m256 vi5 = _mm256_loadu_ps(input + 40);
46 const __m256 vi6 = _mm256_loadu_ps(input + 48);
47 const __m256 vi7 = _mm256_loadu_ps(input + 56);
48 const __m256 vi8 = _mm256_loadu_ps(input + 64);
49 input += 72;
50
51 const __m256 vx0 = _mm256_sub_ps(vi0, vi_max);
52 const __m256 vx1 = _mm256_sub_ps(vi1, vi_max);
53 const __m256 vx2 = _mm256_sub_ps(vi2, vi_max);
54 const __m256 vx3 = _mm256_sub_ps(vi3, vi_max);
55 const __m256 vx4 = _mm256_sub_ps(vi4, vi_max);
56 const __m256 vx5 = _mm256_sub_ps(vi5, vi_max);
57 const __m256 vx6 = _mm256_sub_ps(vi6, vi_max);
58 const __m256 vx7 = _mm256_sub_ps(vi7, vi_max);
59 const __m256 vx8 = _mm256_sub_ps(vi8, vi_max);
60
61 __m256 vn0 = _mm256_fmadd_ps(vx0, vlog2e, vmagic_bias);
62 __m256 vn1 = _mm256_fmadd_ps(vx1, vlog2e, vmagic_bias);
63 __m256 vn2 = _mm256_fmadd_ps(vx2, vlog2e, vmagic_bias);
64 __m256 vn3 = _mm256_fmadd_ps(vx3, vlog2e, vmagic_bias);
65 __m256 vn4 = _mm256_fmadd_ps(vx4, vlog2e, vmagic_bias);
66 __m256 vn5 = _mm256_fmadd_ps(vx5, vlog2e, vmagic_bias);
67 __m256 vn6 = _mm256_fmadd_ps(vx6, vlog2e, vmagic_bias);
68 __m256 vn7 = _mm256_fmadd_ps(vx7, vlog2e, vmagic_bias);
69 __m256 vn8 = _mm256_fmadd_ps(vx8, vlog2e, vmagic_bias);
70
71 const __m256 vs0 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn0), 23));
72 const __m256 vs1 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn1), 23));
73 const __m256 vs2 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn2), 23));
74 const __m256 vs3 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn3), 23));
75 const __m256 vs4 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn4), 23));
76 const __m256 vs5 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn5), 23));
77 const __m256 vs6 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn6), 23));
78 const __m256 vs7 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn7), 23));
79 const __m256 vs8 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn8), 23));
80
81 vn0 = _mm256_sub_ps(vn0, vmagic_bias);
82 vn1 = _mm256_sub_ps(vn1, vmagic_bias);
83 vn2 = _mm256_sub_ps(vn2, vmagic_bias);
84 vn3 = _mm256_sub_ps(vn3, vmagic_bias);
85 vn4 = _mm256_sub_ps(vn4, vmagic_bias);
86 vn5 = _mm256_sub_ps(vn5, vmagic_bias);
87 vn6 = _mm256_sub_ps(vn6, vmagic_bias);
88 vn7 = _mm256_sub_ps(vn7, vmagic_bias);
89 vn8 = _mm256_sub_ps(vn8, vmagic_bias);
90
91 __m256 vt0 = _mm256_fmadd_ps(vn0, vminus_ln2, vx0);
92 __m256 vt1 = _mm256_fmadd_ps(vn1, vminus_ln2, vx1);
93 __m256 vt2 = _mm256_fmadd_ps(vn2, vminus_ln2, vx2);
94 __m256 vt3 = _mm256_fmadd_ps(vn3, vminus_ln2, vx3);
95 __m256 vt4 = _mm256_fmadd_ps(vn4, vminus_ln2, vx4);
96 __m256 vt5 = _mm256_fmadd_ps(vn5, vminus_ln2, vx5);
97 __m256 vt6 = _mm256_fmadd_ps(vn6, vminus_ln2, vx6);
98 __m256 vt7 = _mm256_fmadd_ps(vn7, vminus_ln2, vx7);
99 __m256 vt8 = _mm256_fmadd_ps(vn8, vminus_ln2, vx8);
100
101 __m256 vp0 = _mm256_fmadd_ps(vc5, vt0, vc4);
102 __m256 vp1 = _mm256_fmadd_ps(vc5, vt1, vc4);
103 __m256 vp2 = _mm256_fmadd_ps(vc5, vt2, vc4);
104 __m256 vp3 = _mm256_fmadd_ps(vc5, vt3, vc4);
105 __m256 vp4 = _mm256_fmadd_ps(vc5, vt4, vc4);
106 __m256 vp5 = _mm256_fmadd_ps(vc5, vt5, vc4);
107 __m256 vp6 = _mm256_fmadd_ps(vc5, vt6, vc4);
108 __m256 vp7 = _mm256_fmadd_ps(vc5, vt7, vc4);
109 __m256 vp8 = _mm256_fmadd_ps(vc5, vt8, vc4);
110
111 vp0 = _mm256_fmadd_ps(vp0, vt0, vc3);
112 vp1 = _mm256_fmadd_ps(vp1, vt1, vc3);
113 vp2 = _mm256_fmadd_ps(vp2, vt2, vc3);
114 vp3 = _mm256_fmadd_ps(vp3, vt3, vc3);
115 vp4 = _mm256_fmadd_ps(vp4, vt4, vc3);
116 vp5 = _mm256_fmadd_ps(vp5, vt5, vc3);
117 vp6 = _mm256_fmadd_ps(vp6, vt6, vc3);
118 vp7 = _mm256_fmadd_ps(vp7, vt7, vc3);
119 vp8 = _mm256_fmadd_ps(vp8, vt8, vc3);
120
121 vp0 = _mm256_fmadd_ps(vp0, vt0, vc2);
122 vp1 = _mm256_fmadd_ps(vp1, vt1, vc2);
123 vp2 = _mm256_fmadd_ps(vp2, vt2, vc2);
124 vp3 = _mm256_fmadd_ps(vp3, vt3, vc2);
125 vp4 = _mm256_fmadd_ps(vp4, vt4, vc2);
126 vp5 = _mm256_fmadd_ps(vp5, vt5, vc2);
127 vp6 = _mm256_fmadd_ps(vp6, vt6, vc2);
128 vp7 = _mm256_fmadd_ps(vp7, vt7, vc2);
129 vp8 = _mm256_fmadd_ps(vp8, vt8, vc2);
130
131 vp0 = _mm256_fmadd_ps(vp0, vt0, vc1);
132 vp1 = _mm256_fmadd_ps(vp1, vt1, vc1);
133 vp2 = _mm256_fmadd_ps(vp2, vt2, vc1);
134 vp3 = _mm256_fmadd_ps(vp3, vt3, vc1);
135 vp4 = _mm256_fmadd_ps(vp4, vt4, vc1);
136 vp5 = _mm256_fmadd_ps(vp5, vt5, vc1);
137 vp6 = _mm256_fmadd_ps(vp6, vt6, vc1);
138 vp7 = _mm256_fmadd_ps(vp7, vt7, vc1);
139 vp8 = _mm256_fmadd_ps(vp8, vt8, vc1);
140
141 vt0 = _mm256_mul_ps(vt0, vs0);
142 vt1 = _mm256_mul_ps(vt1, vs1);
143 vt2 = _mm256_mul_ps(vt2, vs2);
144 vt3 = _mm256_mul_ps(vt3, vs3);
145 vt4 = _mm256_mul_ps(vt4, vs4);
146 vt5 = _mm256_mul_ps(vt5, vs5);
147 vt6 = _mm256_mul_ps(vt6, vs6);
148 vt7 = _mm256_mul_ps(vt7, vs7);
149 vt8 = _mm256_mul_ps(vt8, vs8);
150
151 __m256 vf0 = _mm256_fmadd_ps(vt0, vp0, vs0);
152 __m256 vf1 = _mm256_fmadd_ps(vt1, vp1, vs1);
153 __m256 vf2 = _mm256_fmadd_ps(vt2, vp2, vs2);
154 __m256 vf3 = _mm256_fmadd_ps(vt3, vp3, vs3);
155 __m256 vf4 = _mm256_fmadd_ps(vt4, vp4, vs4);
156 __m256 vf5 = _mm256_fmadd_ps(vt5, vp5, vs5);
157 __m256 vf6 = _mm256_fmadd_ps(vt6, vp6, vs6);
158 __m256 vf7 = _mm256_fmadd_ps(vt7, vp7, vs7);
159 __m256 vf8 = _mm256_fmadd_ps(vt8, vp8, vs8);
160
161 vf0 = _mm256_andnot_ps(_mm256_cmp_ps(vx0, vdenorm_cutoff, _CMP_LT_OS), vf0);
162 vf1 = _mm256_andnot_ps(_mm256_cmp_ps(vx1, vdenorm_cutoff, _CMP_LT_OS), vf1);
163 vf2 = _mm256_andnot_ps(_mm256_cmp_ps(vx2, vdenorm_cutoff, _CMP_LT_OS), vf2);
164 vf3 = _mm256_andnot_ps(_mm256_cmp_ps(vx3, vdenorm_cutoff, _CMP_LT_OS), vf3);
165 vf4 = _mm256_andnot_ps(_mm256_cmp_ps(vx4, vdenorm_cutoff, _CMP_LT_OS), vf4);
166 vf5 = _mm256_andnot_ps(_mm256_cmp_ps(vx5, vdenorm_cutoff, _CMP_LT_OS), vf5);
167 vf6 = _mm256_andnot_ps(_mm256_cmp_ps(vx6, vdenorm_cutoff, _CMP_LT_OS), vf6);
168 vf7 = _mm256_andnot_ps(_mm256_cmp_ps(vx7, vdenorm_cutoff, _CMP_LT_OS), vf7);
169 vf8 = _mm256_andnot_ps(_mm256_cmp_ps(vx8, vdenorm_cutoff, _CMP_LT_OS), vf8);
170
171 _mm256_storeu_ps(output, vf0);
172 _mm256_storeu_ps(output + 8, vf1);
173 _mm256_storeu_ps(output + 16, vf2);
174 _mm256_storeu_ps(output + 24, vf3);
175 _mm256_storeu_ps(output + 32, vf4);
176 _mm256_storeu_ps(output + 40, vf5);
177 _mm256_storeu_ps(output + 48, vf6);
178 _mm256_storeu_ps(output + 56, vf7);
179 _mm256_storeu_ps(output + 64, vf8);
180 output += 72;
181
182 vacc0 = _mm256_add_ps(vacc0, vf0);
183 vacc0 = _mm256_add_ps(vacc0, vf1);
184 vacc0 = _mm256_add_ps(vacc0, vf2);
185 vacc0 = _mm256_add_ps(vacc0, vf3);
186 vacc0 = _mm256_add_ps(vacc0, vf4);
187 vacc0 = _mm256_add_ps(vacc0, vf5);
188 vacc0 = _mm256_add_ps(vacc0, vf6);
189 vacc0 = _mm256_add_ps(vacc0, vf7);
190 vacc0 = _mm256_add_ps(vacc0, vf8);
191 }
192
193 __m256 vacc = vacc0;
194 for (; elements >= 8 * sizeof(float); elements -= 8 * sizeof(float)) {
195 const __m256 vi = _mm256_loadu_ps(input);
196 input += 8;
197
198 const __m256 vx = _mm256_sub_ps(vi, vi_max);
199
200 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
201
202 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
203
204 vn = _mm256_sub_ps(vn, vmagic_bias);
205
206 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
207
208 __m256 vp = _mm256_fmadd_ps(vc5, vt, vc4);
209 vp = _mm256_fmadd_ps(vp, vt, vc3);
210 vp = _mm256_fmadd_ps(vp, vt, vc2);
211 vp = _mm256_fmadd_ps(vp, vt, vc1);
212
213 vt = _mm256_mul_ps(vt, vs);
214 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
215
216 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
217
218 _mm256_storeu_ps(output, vf);
219 output += 8;
220
221 vacc = _mm256_add_ps(vacc, vf);
222 }
223 if (elements != 0) {
224 assert(elements >= 1 * sizeof(float));
225 assert(elements <= 7 * sizeof(float));
226 const __m256i vmask = _mm256_loadu_si256((const __m256i*) ((uintptr_t) ¶ms->avx2_rr1_p5.mask_table[7] - elements));
227
228 const __m256 vi = _mm256_maskload_ps(input, vmask);
229
230 const __m256 vx = _mm256_sub_ps(vi, vi_max);
231
232 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
233
234 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
235
236 vn = _mm256_sub_ps(vn, vmagic_bias);
237
238 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
239
240 __m256 vp = _mm256_fmadd_ps(vc5, vt, vc4);
241 vp = _mm256_fmadd_ps(vp, vt, vc3);
242 vp = _mm256_fmadd_ps(vp, vt, vc2);
243 vp = _mm256_fmadd_ps(vp, vt, vc1);
244
245 vt = _mm256_mul_ps(vt, vs);
246 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
247
248 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
249
250 __m128 vf_lo = _mm256_castps256_ps128(vf);
251 if (elements & (4 * sizeof(float))) {
252 _mm_storeu_ps(output, vf_lo);
253 vf_lo = _mm256_extractf128_ps(vf, 1);
254 output += 4;
255 }
256 if (elements & (2 * sizeof(float))) {
257 _mm_storel_pi((__m64*) output, vf_lo);
258 vf_lo = _mm_movehl_ps(vf_lo, vf_lo);
259 output += 2;
260 }
261 if (elements & (1 * sizeof(float))) {
262 _mm_store_ss(output, vf_lo);
263 }
264
265 vacc = _mm256_add_ps(vacc, _mm256_and_ps(vf, _mm256_castsi256_ps(vmask)));
266 }
267 __m128 vacc_lo = _mm_add_ps(_mm256_castps256_ps128(vacc), _mm256_extractf128_ps(vacc, 1));
268 vacc_lo = _mm_add_ps(vacc_lo, _mm_movehl_ps(vacc_lo, vacc_lo));
269 vacc_lo = _mm_add_ss(vacc_lo, _mm_movehdup_ps(vacc_lo));
270 _mm_store_ss(sum, vacc_lo);
271 _mm256_zeroupper();
272 }
273