1// Copyright 2020 Google LLC 2// 3// This source code is licensed under the BSD-style license found in the 4// LICENSE file in the root directory of this source tree. 5 6$assert NR == 2 7$assert MR % 2 == 0 8$assert ACTIVATION != "MINMAX" or ARCH in ["ARM", "X86", "RELAXED"] 9$assert not FMA or ARCH == "RELAXED" 10#include <assert.h> 11 12#include <wasm_simd128.h> 13 14#include <xnnpack/gemm.h> 15 16 17$assert ACTIVATION in ["LINEAR", "RELU", "MINMAX"] 18$if ACTIVATION == "MINMAX": 19$ WASM_F32X4_MIN={"ARM": "wasm_f32x4_min", "X86": "wasm_f32x4_pmin", "RELAXED": "__builtin_wasm_relaxed_min_f32x4"}[ARCH] 20$ WASM_F32X4_MAX={"ARM": "wasm_f32x4_max", "X86": "wasm_f32x4_pmax", "RELAXED": "__builtin_wasm_relaxed_max_f32x4"}[ARCH] 21$ACTIVATION_SUFFIX = {"LINEAR": ""}.get(ACTIVATION, "_" + ACTIVATION.lower()) 22$ISA = "wasmsimd" if not FMA and (ACTIVATION in ["LINEAR", "RELU"] or ARCH != "RELAXED") else "wasmrelaxedsimd" 23$ARCH_SUFFIX = "" if not FMA and (ACTIVATION in ["LINEAR", "RELU"] or ARCH == "RELAXED") else "_" + ("fma" if FMA else ARCH.lower()) 24$PARAMS = {"LINEAR": "xnn_f32_default_params", "RELU": "xnn_f32_relu_params", "MINMAX": "xnn_f32_minmax_params"}[ACTIVATION] 25void xnn_f32_gemm${ACTIVATION_SUFFIX}_ukernel_${MR}x${NR}c4__${ISA}${ARCH_SUFFIX}( 26 size_t mr, 27 size_t nc, 28 size_t kc, 29 const float* restrict a, 30 size_t a_stride, 31 const float* restrict w, 32 float* restrict c, 33 size_t cm_stride, 34 size_t cn_stride, 35 const union ${PARAMS} params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS 36{ 37 assert(mr != 0); 38 assert(mr <= ${MR}); 39 assert(nc != 0); 40 assert(kc != 0); 41 assert(kc % sizeof(float) == 0); 42 assert(a != NULL); 43 assert(w != NULL); 44 assert(c != NULL); 45 46 const float* a0 = a; 47 float* c0 = c; 48 $for M in range(1, MR): 49 const float* a${M} = (const float*) ((uintptr_t) a${M-1} + a_stride); 50 float* c${M} = (float*) ((uintptr_t) c${M-1} + cm_stride); 51 $if M % 2 == 0: 52 if XNN_UNPREDICTABLE(mr <= ${M}) { 53 a${M} = a${M-1}; 54 c${M} = c${M-1}; 55 } 56 $elif M + 1 == MR: 57 if XNN_UNPREDICTABLE(mr != ${M+1}) { 58 a${M} = a${M-1}; 59 c${M} = c${M-1}; 60 } 61 $else: 62 if XNN_UNPREDICTABLE(mr < ${M+1}) { 63 a${M} = a${M-1}; 64 c${M} = c${M-1}; 65 } 66 67 $if ACTIVATION == "MINMAX": 68 const v128_t vmin = wasm_v128_load64_splat(params->wasmsimd.min); 69 const v128_t vmax = wasm_v128_load64_splat(params->wasmsimd.max); 70 do { 71 v128_t vacc0x0c4 = wasm_f32x4_replace_lane(wasm_f32x4_const_splat(0.0f), 0, w[0]); 72 $for N in range(1, NR): 73 v128_t vacc0x${N}c4 = wasm_f32x4_replace_lane(vacc0x0c4, 0, w[${N}]); 74 $for M in range(1, MR): 75 $for N in range(NR): 76 v128_t vacc${M}x${N}c4 = vacc0x${N}c4; 77 w += ${NR}; 78 79 size_t k = kc; 80 for (; k >= 4 * sizeof(float); k -= 4 * sizeof(float)) { 81 $for M in range(MR): 82 const v128_t va${M} = wasm_v128_load(a${M}); 83 a${M} += 4; 84 85 const v128_t vb0 = wasm_v128_load(w); 86 $for N in range(1, NR): 87 const v128_t vb${N} = wasm_v128_load(w + ${N * 4}); 88 w += ${NR * 4}; 89 90 $for M in range(MR): 91 $for N in range(NR): 92 $if FMA: 93 vacc${M}x${N}c4 = __builtin_wasm_fma_f32x4(vacc${M}x${N}c4, va${M}, vb${N}); 94 $else: 95 vacc${M}x${N}c4 = wasm_f32x4_add(vacc${M}x${N}c4, wasm_f32x4_mul(va${M}, vb${N})); 96 } 97 if XNN_UNLIKELY(k != 0) { 98 $for M in range(MR): 99 const v128_t va${M} = wasm_v128_load(a${M}); 100 a${M} = (const float*) ((uintptr_t) a${M} + k); 101 102 const v128_t vb0 = wasm_v128_load(w); 103 $for N in range(1, NR): 104 const v128_t vb${N} = wasm_v128_load(w + ${N * 4}); 105 w += ${NR * 4}; 106 107 const v128_t vzero = wasm_f32x4_const_splat(0.0f); 108 $for N in range(NR): 109 const v128_t vmask${N} = wasm_f32x4_eq(vb${N}, vzero); 110 111 $for M in range(MR): 112 $for N in range(NR): 113 $if FMA: 114 vacc${M}x${N}c4 = __builtin_wasm_fma_f32x4(vacc${M}x${N}c4, wasm_v128_andnot(va${M}, vmask${N}), vb${N}); 115 $else: 116 vacc${M}x${N}c4 = wasm_f32x4_add(vacc${M}x${N}c4, wasm_f32x4_mul(wasm_v128_andnot(va${M}, vmask${N}), vb${N})); 117 } 118 119 $for M in range(MR): 120 const v128_t vacc${M}x01c2 = wasm_f32x4_add( 121 wasm_v32x4_shuffle(vacc${M}x0c4, vacc${M}x1c4, 0, 4, 1, 5), 122 wasm_v32x4_shuffle(vacc${M}x0c4, vacc${M}x1c4, 2, 6, 3, 7)); 123 124 $for M in range(0, MR, 2): 125 v128_t vacc${M}${M+1}x01 = wasm_f32x4_add( 126 wasm_v32x4_shuffle(vacc${M}x01c2, vacc${M+1}x01c2, 0, 1, 4, 5), 127 wasm_v32x4_shuffle(vacc${M}x01c2, vacc${M+1}x01c2, 2, 3, 6, 7)); 128 129 $if ACTIVATION == "MINMAX": 130 $for M in range(0, MR, 2): 131 vacc${M}${M+1}x01 = ${WASM_F32X4_MAX}(vmin, vacc${M}${M+1}x01); 132 133 $for M in range(0, MR, 2): 134 vacc${M}${M+1}x01 = ${WASM_F32X4_MIN}(vmax, vacc${M}${M+1}x01); 135 $elif ACTIVATION == "RELU": 136 const v128_t vzero = wasm_i32x4_const_splat(0); 137 $for M in range(0, MR, 2): 138 vacc${M}${M+1}x01 = wasm_i32x4_max(vacc${M}${M+1}x01, vzero); 139 140 if XNN_LIKELY(nc >= ${NR}) { 141 $for M in reversed(range(0, MR, 2)): 142 *((double*) c${M}) = wasm_f64x2_extract_lane(vacc${M}${M+1}x01, 0); 143 c${M} = (float*) ((uintptr_t) c${M} + cn_stride); 144 a${M} = (const float*) ((uintptr_t) a${M} - kc); 145 *((double*) c${M+1}) = wasm_f64x2_extract_lane(vacc${M}${M+1}x01, 1); 146 c${M+1} = (float*) ((uintptr_t) c${M+1} + cn_stride); 147 a${M+1} = (const float*) ((uintptr_t) a${M+1} - kc); 148 149 nc -= ${NR}; 150 } else { 151 assert(nc == 1); 152 $for M in reversed(range(0, MR, 2)): 153 *c${M} = wasm_f32x4_extract_lane(vacc${M}${M+1}x01, 0); 154 *c${M+1} = wasm_f32x4_extract_lane(vacc${M}${M+1}x01, 2); 155 156 nc = 0; 157 } 158 } while (nc != 0); 159} 160