1 // Auto-generated file. Do not edit!
2 // Template: src/f16-raddstoreexpminusmax/avx2-rr1-p2.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2022 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/intrinsics-polyfill.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f16_raddstoreexpminusmax_ukernel__avx2_rr1_p2_x64_acc2(size_t batch,const void * input,const void * max,void * output,void * sum,const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f16_raddstoreexpminusmax_ukernel__avx2_rr1_p2_x64_acc2(
19 size_t batch,
20 const void* input,
21 const void* max,
22 void* output,
23 void* sum,
24 const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26 assert(batch % sizeof(uint16_t) == 0);
27
28 const __m256 vi_max = _mm256_cvtph_ps(_mm_set1_epi16((short) *((const uint16_t*) max)));
29 const __m256 vlog2e = _mm256_load_ps(params->avx2_rr1_p2.log2e);
30 const __m256 vmagic_bias = _mm256_load_ps(params->avx2_rr1_p2.magic_bias);
31 const __m256 vminus_ln2 = _mm256_load_ps(params->avx2_rr1_p2.minus_ln2);
32 const __m256 vc2 = _mm256_load_ps(params->avx2_rr1_p2.c2);
33 const __m256 vc1 = _mm256_load_ps(params->avx2_rr1_p2.c1);
34 const __m256 vdenorm_cutoff = _mm256_load_ps(params->avx2_rr1_p2.denorm_cutoff);
35
36 const uint16_t* i = (const uint16_t*) input;
37 uint16_t* o = (uint16_t*) output;
38 __m256 vacc0 = _mm256_setzero_ps();
39 __m256 vacc1 = _mm256_setzero_ps();
40 for (; batch >= 64 * sizeof(uint16_t); batch -= 64 * sizeof(uint16_t)) {
41 const __m256 vi0 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
42 const __m256 vi1 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 8)));
43 const __m256 vi2 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 16)));
44 const __m256 vi3 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 24)));
45 const __m256 vi4 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 32)));
46 const __m256 vi5 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 40)));
47 const __m256 vi6 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 48)));
48 const __m256 vi7 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 56)));
49 i += 64;
50
51 const __m256 vx0 = _mm256_sub_ps(vi0, vi_max);
52 const __m256 vx1 = _mm256_sub_ps(vi1, vi_max);
53 const __m256 vx2 = _mm256_sub_ps(vi2, vi_max);
54 const __m256 vx3 = _mm256_sub_ps(vi3, vi_max);
55 const __m256 vx4 = _mm256_sub_ps(vi4, vi_max);
56 const __m256 vx5 = _mm256_sub_ps(vi5, vi_max);
57 const __m256 vx6 = _mm256_sub_ps(vi6, vi_max);
58 const __m256 vx7 = _mm256_sub_ps(vi7, vi_max);
59
60 __m256 vn0 = _mm256_fmadd_ps(vx0, vlog2e, vmagic_bias);
61 __m256 vn1 = _mm256_fmadd_ps(vx1, vlog2e, vmagic_bias);
62 __m256 vn2 = _mm256_fmadd_ps(vx2, vlog2e, vmagic_bias);
63 __m256 vn3 = _mm256_fmadd_ps(vx3, vlog2e, vmagic_bias);
64 __m256 vn4 = _mm256_fmadd_ps(vx4, vlog2e, vmagic_bias);
65 __m256 vn5 = _mm256_fmadd_ps(vx5, vlog2e, vmagic_bias);
66 __m256 vn6 = _mm256_fmadd_ps(vx6, vlog2e, vmagic_bias);
67 __m256 vn7 = _mm256_fmadd_ps(vx7, vlog2e, vmagic_bias);
68
69 const __m256 vs0 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn0), 23));
70 const __m256 vs1 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn1), 23));
71 const __m256 vs2 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn2), 23));
72 const __m256 vs3 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn3), 23));
73 const __m256 vs4 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn4), 23));
74 const __m256 vs5 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn5), 23));
75 const __m256 vs6 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn6), 23));
76 const __m256 vs7 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn7), 23));
77
78 vn0 = _mm256_sub_ps(vn0, vmagic_bias);
79 vn1 = _mm256_sub_ps(vn1, vmagic_bias);
80 vn2 = _mm256_sub_ps(vn2, vmagic_bias);
81 vn3 = _mm256_sub_ps(vn3, vmagic_bias);
82 vn4 = _mm256_sub_ps(vn4, vmagic_bias);
83 vn5 = _mm256_sub_ps(vn5, vmagic_bias);
84 vn6 = _mm256_sub_ps(vn6, vmagic_bias);
85 vn7 = _mm256_sub_ps(vn7, vmagic_bias);
86
87 __m256 vt0 = _mm256_fmadd_ps(vn0, vminus_ln2, vx0);
88 __m256 vt1 = _mm256_fmadd_ps(vn1, vminus_ln2, vx1);
89 __m256 vt2 = _mm256_fmadd_ps(vn2, vminus_ln2, vx2);
90 __m256 vt3 = _mm256_fmadd_ps(vn3, vminus_ln2, vx3);
91 __m256 vt4 = _mm256_fmadd_ps(vn4, vminus_ln2, vx4);
92 __m256 vt5 = _mm256_fmadd_ps(vn5, vminus_ln2, vx5);
93 __m256 vt6 = _mm256_fmadd_ps(vn6, vminus_ln2, vx6);
94 __m256 vt7 = _mm256_fmadd_ps(vn7, vminus_ln2, vx7);
95
96 const __m256 vp0 = _mm256_fmadd_ps(vc2, vt0, vc1);
97 const __m256 vp1 = _mm256_fmadd_ps(vc2, vt1, vc1);
98 const __m256 vp2 = _mm256_fmadd_ps(vc2, vt2, vc1);
99 const __m256 vp3 = _mm256_fmadd_ps(vc2, vt3, vc1);
100 const __m256 vp4 = _mm256_fmadd_ps(vc2, vt4, vc1);
101 const __m256 vp5 = _mm256_fmadd_ps(vc2, vt5, vc1);
102 const __m256 vp6 = _mm256_fmadd_ps(vc2, vt6, vc1);
103 const __m256 vp7 = _mm256_fmadd_ps(vc2, vt7, vc1);
104
105 vt0 = _mm256_mul_ps(vt0, vs0);
106 vt1 = _mm256_mul_ps(vt1, vs1);
107 vt2 = _mm256_mul_ps(vt2, vs2);
108 vt3 = _mm256_mul_ps(vt3, vs3);
109 vt4 = _mm256_mul_ps(vt4, vs4);
110 vt5 = _mm256_mul_ps(vt5, vs5);
111 vt6 = _mm256_mul_ps(vt6, vs6);
112 vt7 = _mm256_mul_ps(vt7, vs7);
113
114 __m256 vf0 = _mm256_fmadd_ps(vt0, vp0, vs0);
115 __m256 vf1 = _mm256_fmadd_ps(vt1, vp1, vs1);
116 __m256 vf2 = _mm256_fmadd_ps(vt2, vp2, vs2);
117 __m256 vf3 = _mm256_fmadd_ps(vt3, vp3, vs3);
118 __m256 vf4 = _mm256_fmadd_ps(vt4, vp4, vs4);
119 __m256 vf5 = _mm256_fmadd_ps(vt5, vp5, vs5);
120 __m256 vf6 = _mm256_fmadd_ps(vt6, vp6, vs6);
121 __m256 vf7 = _mm256_fmadd_ps(vt7, vp7, vs7);
122
123 vf0 = _mm256_andnot_ps(_mm256_cmp_ps(vx0, vdenorm_cutoff, _CMP_LT_OS), vf0);
124 vf1 = _mm256_andnot_ps(_mm256_cmp_ps(vx1, vdenorm_cutoff, _CMP_LT_OS), vf1);
125 vf2 = _mm256_andnot_ps(_mm256_cmp_ps(vx2, vdenorm_cutoff, _CMP_LT_OS), vf2);
126 vf3 = _mm256_andnot_ps(_mm256_cmp_ps(vx3, vdenorm_cutoff, _CMP_LT_OS), vf3);
127 vf4 = _mm256_andnot_ps(_mm256_cmp_ps(vx4, vdenorm_cutoff, _CMP_LT_OS), vf4);
128 vf5 = _mm256_andnot_ps(_mm256_cmp_ps(vx5, vdenorm_cutoff, _CMP_LT_OS), vf5);
129 vf6 = _mm256_andnot_ps(_mm256_cmp_ps(vx6, vdenorm_cutoff, _CMP_LT_OS), vf6);
130 vf7 = _mm256_andnot_ps(_mm256_cmp_ps(vx7, vdenorm_cutoff, _CMP_LT_OS), vf7);
131
132 _mm_storeu_si128((__m128i*) o, _mm256_cvtps_ph(vf0, _MM_FROUND_NO_EXC));
133 _mm_storeu_si128((__m128i*) (o + 8), _mm256_cvtps_ph(vf1, _MM_FROUND_NO_EXC));
134 _mm_storeu_si128((__m128i*) (o + 16), _mm256_cvtps_ph(vf2, _MM_FROUND_NO_EXC));
135 _mm_storeu_si128((__m128i*) (o + 24), _mm256_cvtps_ph(vf3, _MM_FROUND_NO_EXC));
136 _mm_storeu_si128((__m128i*) (o + 32), _mm256_cvtps_ph(vf4, _MM_FROUND_NO_EXC));
137 _mm_storeu_si128((__m128i*) (o + 40), _mm256_cvtps_ph(vf5, _MM_FROUND_NO_EXC));
138 _mm_storeu_si128((__m128i*) (o + 48), _mm256_cvtps_ph(vf6, _MM_FROUND_NO_EXC));
139 _mm_storeu_si128((__m128i*) (o + 56), _mm256_cvtps_ph(vf7, _MM_FROUND_NO_EXC));
140 o += 64;
141
142 vacc0 = _mm256_add_ps(vacc0, vf0);
143 vacc1 = _mm256_add_ps(vacc1, vf1);
144 vacc0 = _mm256_add_ps(vacc0, vf2);
145 vacc1 = _mm256_add_ps(vacc1, vf3);
146 vacc0 = _mm256_add_ps(vacc0, vf4);
147 vacc1 = _mm256_add_ps(vacc1, vf5);
148 vacc0 = _mm256_add_ps(vacc0, vf6);
149 vacc1 = _mm256_add_ps(vacc1, vf7);
150 }
151 vacc0 = _mm256_add_ps(vacc0, vacc1);
152
153 __m256 vacc = vacc0;
154 for (; batch >= 8 * sizeof(uint16_t); batch -= 8 * sizeof(uint16_t)) {
155 const __m256 vi = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
156 i += 8;
157
158 const __m256 vx = _mm256_sub_ps(vi, vi_max);
159
160 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
161
162 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
163
164 vn = _mm256_sub_ps(vn, vmagic_bias);
165
166 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
167
168 const __m256 vp = _mm256_fmadd_ps(vc2, vt, vc1);
169 vt = _mm256_mul_ps(vt, vs);
170 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
171 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
172
173 _mm_storeu_si128((__m128i*) o, _mm256_cvtps_ph(vf, _MM_FROUND_NO_EXC));
174 o += 8;
175
176 vacc = _mm256_add_ps(vacc, vf);
177 }
178 __m128 vacc_lo = _mm_add_ps(_mm256_castps256_ps128(vacc), _mm256_extractf128_ps(vacc, 1));
179 if (batch != 0) {
180 assert(batch >= 1 * sizeof(uint16_t));
181 assert(batch <= 7 * sizeof(uint16_t));
182
183 const __m256 vi = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
184
185 const __m256 vx = _mm256_sub_ps(vi, vi_max);
186
187 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
188
189 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
190
191 vn = _mm256_sub_ps(vn, vmagic_bias);
192
193 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
194
195 const __m256 vp = _mm256_fmadd_ps(vc2, vt, vc1);
196 vt = _mm256_mul_ps(vt, vs);
197 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
198 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
199
200 __m128i vh = _mm256_cvtps_ph(vf, _MM_FROUND_NO_EXC);
201 __m128 vf_lo = _mm256_castps256_ps128(vf);
202 if (batch & (4 * sizeof(uint16_t))) {
203 _mm_storel_epi64((__m128i*) o, vh);
204 vh = _mm_unpackhi_epi64(vh, vh);
205 vacc_lo = _mm_add_ps(vacc_lo, vf_lo);
206 vf_lo = _mm256_extractf128_ps(vf, 1);
207 o += 4;
208 }
209 if (batch & (2 * sizeof(uint16_t))) {
210 _mm_storeu_si32(o, vh);
211 vh = _mm_srli_epi64(vh, 32);
212 vacc_lo = _mm_blend_ps(_mm_add_ps(vacc_lo, vf_lo), vacc_lo, 0xC);
213 vf_lo = _mm_movehl_ps(vf_lo, vf_lo);
214 o += 2;
215 }
216 if (batch & (1 * sizeof(uint16_t))) {
217 *o = (uint16_t) _mm_extract_epi16(vh, 0);
218 vacc_lo = _mm_add_ss(vacc_lo, vf_lo);
219 }
220 }
221 vacc_lo = _mm_add_ps(vacc_lo, _mm_movehl_ps(vacc_lo, vacc_lo));
222 vacc_lo = _mm_add_ss(vacc_lo, _mm_movehdup_ps(vacc_lo));
223 *((uint16_t*) sum) = (uint16_t) _mm_extract_epi16(_mm_cvtps_ph(vacc_lo, _MM_FROUND_NO_EXC), 0);
224 _mm256_zeroupper();
225 }
226