xref: /aosp_15_r20/external/XNNPACK/src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x32.c (revision 4bdc94577ba0e567308109d787f7fec7b531ce36)
1 // Auto-generated file. Do not edit!
2 //   Template: src/f16-raddstoreexpminusmax/avx2-rr1-p2.c.in
3 //   Generator: tools/xngen
4 //
5 // Copyright 2022 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9 
10 #include <assert.h>
11 
12 #include <immintrin.h>
13 
14 #include <xnnpack/intrinsics-polyfill.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16 
17 
xnn_f16_raddstoreexpminusmax_ukernel__avx2_rr1_p2_x32(size_t batch,const void * input,const void * max,void * output,void * sum,const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f16_raddstoreexpminusmax_ukernel__avx2_rr1_p2_x32(
19     size_t batch,
20     const void* input,
21     const void* max,
22     void* output,
23     void* sum,
24     const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26   assert(batch % sizeof(uint16_t) == 0);
27 
28   const __m256 vi_max = _mm256_cvtph_ps(_mm_set1_epi16((short) *((const uint16_t*) max)));
29   const __m256 vlog2e = _mm256_load_ps(params->avx2_rr1_p2.log2e);
30   const __m256 vmagic_bias = _mm256_load_ps(params->avx2_rr1_p2.magic_bias);
31   const __m256 vminus_ln2 = _mm256_load_ps(params->avx2_rr1_p2.minus_ln2);
32   const __m256 vc2 = _mm256_load_ps(params->avx2_rr1_p2.c2);
33   const __m256 vc1 = _mm256_load_ps(params->avx2_rr1_p2.c1);
34   const __m256 vdenorm_cutoff = _mm256_load_ps(params->avx2_rr1_p2.denorm_cutoff);
35 
36   const uint16_t* i = (const uint16_t*) input;
37   uint16_t* o = (uint16_t*) output;
38   __m256 vacc0 = _mm256_setzero_ps();
39   for (; batch >= 32 * sizeof(uint16_t); batch -= 32 * sizeof(uint16_t)) {
40     const __m256 vi0 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
41     const __m256 vi1 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 8)));
42     const __m256 vi2 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 16)));
43     const __m256 vi3 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 24)));
44     i += 32;
45 
46     const __m256 vx0 = _mm256_sub_ps(vi0, vi_max);
47     const __m256 vx1 = _mm256_sub_ps(vi1, vi_max);
48     const __m256 vx2 = _mm256_sub_ps(vi2, vi_max);
49     const __m256 vx3 = _mm256_sub_ps(vi3, vi_max);
50 
51     __m256 vn0 = _mm256_fmadd_ps(vx0, vlog2e, vmagic_bias);
52     __m256 vn1 = _mm256_fmadd_ps(vx1, vlog2e, vmagic_bias);
53     __m256 vn2 = _mm256_fmadd_ps(vx2, vlog2e, vmagic_bias);
54     __m256 vn3 = _mm256_fmadd_ps(vx3, vlog2e, vmagic_bias);
55 
56     const __m256 vs0 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn0), 23));
57     const __m256 vs1 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn1), 23));
58     const __m256 vs2 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn2), 23));
59     const __m256 vs3 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn3), 23));
60 
61     vn0 = _mm256_sub_ps(vn0, vmagic_bias);
62     vn1 = _mm256_sub_ps(vn1, vmagic_bias);
63     vn2 = _mm256_sub_ps(vn2, vmagic_bias);
64     vn3 = _mm256_sub_ps(vn3, vmagic_bias);
65 
66     __m256 vt0 = _mm256_fmadd_ps(vn0, vminus_ln2, vx0);
67     __m256 vt1 = _mm256_fmadd_ps(vn1, vminus_ln2, vx1);
68     __m256 vt2 = _mm256_fmadd_ps(vn2, vminus_ln2, vx2);
69     __m256 vt3 = _mm256_fmadd_ps(vn3, vminus_ln2, vx3);
70 
71     const __m256 vp0 = _mm256_fmadd_ps(vc2, vt0, vc1);
72     const __m256 vp1 = _mm256_fmadd_ps(vc2, vt1, vc1);
73     const __m256 vp2 = _mm256_fmadd_ps(vc2, vt2, vc1);
74     const __m256 vp3 = _mm256_fmadd_ps(vc2, vt3, vc1);
75 
76     vt0 = _mm256_mul_ps(vt0, vs0);
77     vt1 = _mm256_mul_ps(vt1, vs1);
78     vt2 = _mm256_mul_ps(vt2, vs2);
79     vt3 = _mm256_mul_ps(vt3, vs3);
80 
81     __m256 vf0 = _mm256_fmadd_ps(vt0, vp0, vs0);
82     __m256 vf1 = _mm256_fmadd_ps(vt1, vp1, vs1);
83     __m256 vf2 = _mm256_fmadd_ps(vt2, vp2, vs2);
84     __m256 vf3 = _mm256_fmadd_ps(vt3, vp3, vs3);
85 
86     vf0 = _mm256_andnot_ps(_mm256_cmp_ps(vx0, vdenorm_cutoff, _CMP_LT_OS), vf0);
87     vf1 = _mm256_andnot_ps(_mm256_cmp_ps(vx1, vdenorm_cutoff, _CMP_LT_OS), vf1);
88     vf2 = _mm256_andnot_ps(_mm256_cmp_ps(vx2, vdenorm_cutoff, _CMP_LT_OS), vf2);
89     vf3 = _mm256_andnot_ps(_mm256_cmp_ps(vx3, vdenorm_cutoff, _CMP_LT_OS), vf3);
90 
91     _mm_storeu_si128((__m128i*) o, _mm256_cvtps_ph(vf0, _MM_FROUND_NO_EXC));
92     _mm_storeu_si128((__m128i*) (o + 8), _mm256_cvtps_ph(vf1, _MM_FROUND_NO_EXC));
93     _mm_storeu_si128((__m128i*) (o + 16), _mm256_cvtps_ph(vf2, _MM_FROUND_NO_EXC));
94     _mm_storeu_si128((__m128i*) (o + 24), _mm256_cvtps_ph(vf3, _MM_FROUND_NO_EXC));
95     o += 32;
96 
97     vacc0 = _mm256_add_ps(vacc0, vf0);
98     vacc0 = _mm256_add_ps(vacc0, vf1);
99     vacc0 = _mm256_add_ps(vacc0, vf2);
100     vacc0 = _mm256_add_ps(vacc0, vf3);
101   }
102 
103   __m256 vacc = vacc0;
104   for (; batch >= 8 * sizeof(uint16_t); batch -= 8 * sizeof(uint16_t)) {
105     const __m256 vi = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
106     i += 8;
107 
108     const __m256 vx = _mm256_sub_ps(vi, vi_max);
109 
110     __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
111 
112     const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
113 
114     vn = _mm256_sub_ps(vn, vmagic_bias);
115 
116     __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
117 
118     const __m256 vp = _mm256_fmadd_ps(vc2, vt, vc1);
119     vt = _mm256_mul_ps(vt, vs);
120     __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
121     vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
122 
123     _mm_storeu_si128((__m128i*) o, _mm256_cvtps_ph(vf, _MM_FROUND_NO_EXC));
124     o += 8;
125 
126     vacc = _mm256_add_ps(vacc, vf);
127   }
128   __m128 vacc_lo = _mm_add_ps(_mm256_castps256_ps128(vacc), _mm256_extractf128_ps(vacc, 1));
129   if (batch != 0) {
130     assert(batch >= 1 * sizeof(uint16_t));
131     assert(batch <= 7 * sizeof(uint16_t));
132 
133     const __m256 vi = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
134 
135     const __m256 vx = _mm256_sub_ps(vi, vi_max);
136 
137     __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
138 
139     const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
140 
141     vn = _mm256_sub_ps(vn, vmagic_bias);
142 
143     __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
144 
145     const __m256 vp = _mm256_fmadd_ps(vc2, vt, vc1);
146     vt = _mm256_mul_ps(vt, vs);
147     __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
148     vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
149 
150     __m128i vh = _mm256_cvtps_ph(vf, _MM_FROUND_NO_EXC);
151     __m128 vf_lo = _mm256_castps256_ps128(vf);
152     if (batch & (4 * sizeof(uint16_t))) {
153       _mm_storel_epi64((__m128i*) o, vh);
154       vh = _mm_unpackhi_epi64(vh, vh);
155       vacc_lo = _mm_add_ps(vacc_lo, vf_lo);
156       vf_lo = _mm256_extractf128_ps(vf, 1);
157       o += 4;
158     }
159     if (batch & (2 * sizeof(uint16_t))) {
160       _mm_storeu_si32(o, vh);
161       vh = _mm_srli_epi64(vh, 32);
162       vacc_lo = _mm_blend_ps(_mm_add_ps(vacc_lo, vf_lo), vacc_lo, 0xC);
163       vf_lo = _mm_movehl_ps(vf_lo, vf_lo);
164       o += 2;
165     }
166     if (batch & (1 * sizeof(uint16_t))) {
167       *o = (uint16_t) _mm_extract_epi16(vh, 0);
168       vacc_lo = _mm_add_ss(vacc_lo, vf_lo);
169     }
170   }
171   vacc_lo = _mm_add_ps(vacc_lo, _mm_movehl_ps(vacc_lo, vacc_lo));
172   vacc_lo = _mm_add_ss(vacc_lo, _mm_movehdup_ps(vacc_lo));
173   *((uint16_t*) sum) = (uint16_t) _mm_extract_epi16(_mm_cvtps_ph(vacc_lo, _MM_FROUND_NO_EXC), 0);
174   _mm256_zeroupper();
175 }
176