1// Copyright 2021 Google LLC 2// 3// This source code is licensed under the BSD-style license found in the 4// LICENSE file in the root directory of this source tree. 5 6$assert BATCH_TILE % 8 == 0 7$assert BATCH_TILE >= 8 8$SIMD_TILE = BATCH_TILE // 8 9$ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ" 10#include <assert.h> 11 12#include <arm_neon.h> 13 14#include <xnnpack/common.h> 15#include <xnnpack/vcvt.h> 16 17 18void xnn_f16_f32_vcvt_ukernel__neon_int32_x${BATCH_TILE}( 19 size_t n, 20 const void* input, 21 float* output, 22 const union xnn_f16_f32_cvt_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS 23{ 24 assert(n != 0); 25 assert(n % sizeof(uint16_t) == 0); 26 assert(input != NULL); 27 assert(output != NULL); 28 29 const uint32x4_t vsign_mask = vmovq_n_u32(0x80000000); 30 const uint32x4_t vexp_offset = vmovq_n_u32(0x70000000); 31 const float32x4_t vexp_scale = vld1q_dup_f32(¶ms->neon.exp_scale); 32 const uint32x4_t vmagic_bias = vmovq_n_u32(0x3F000000); 33 const uint32x4_t vdenorm_cutoff = vmovq_n_u32(0x04000000); 34 35 const uint16_t* i = (const uint16_t*) input; 36 $if BATCH_TILE > 8: 37 for (; n >= ${BATCH_TILE} * sizeof(uint16_t); n -= ${BATCH_TILE} * sizeof(uint16_t)) { 38 $for N in range(SIMD_TILE): 39 const uint16x8_t vh${N} = vld1q_u16(i); i += 8; 40 41 $for N in range(SIMD_TILE): 42 const uint32x4_t vw${2*N} = vshll_n_u16(vget_low_u16(vh${N}), 16); 43 const uint32x4_t vw${2*N+1} = vshll_n_u16(vget_high_u16(vh${N}), 16); 44 45 $for N in range(2*SIMD_TILE): 46 const uint32x4_t vsign${N} = vandq_u32(vw${N}, vsign_mask); 47 48 $for N in range(2*SIMD_TILE): 49 const uint32x4_t vnonsign${N} = veorq_u32(vw${N}, vsign${N}); 50 51 $for N in range(2*SIMD_TILE): 52 const float32x4_t vnorm${N} = vmulq_f32(vreinterpretq_f32_u32(vsraq_n_u32(vexp_offset, vnonsign${N}, 3)), vexp_scale); 53 54 $for N in range(2*SIMD_TILE): 55 const float32x4_t vdenorm${N} = vsubq_f32(vreinterpretq_f32_u32(vsriq_n_u32(vmagic_bias, vnonsign${N}, 16)), vreinterpretq_f32_u32(vmagic_bias)); 56 57 $for N in range(2*SIMD_TILE): 58 const uint32x4_t vxmask${N} = vcgtq_u32(vnonsign${N}, vdenorm_cutoff); 59 60 $for N in range(2*SIMD_TILE): 61 const uint32x4_t vf${N} = vorrq_u32(vsign${N}, vreinterpretq_u32_f32(vbslq_f32(vxmask${N}, vnorm${N}, vdenorm${N}))); 62 63 $for N in range(2*SIMD_TILE): 64 vst1q_f32(output, vreinterpretq_f32_u32(vf${N})); output += 4; 65 } 66 for (; n >= 8 * sizeof(uint16_t); n -= 8 * sizeof(uint16_t)) { 67 const uint16x8_t vh = vld1q_u16(i); i += 8; 68 69 const uint32x4_t vw_lo = vshll_n_u16(vget_low_u16(vh), 16); 70 const uint32x4_t vw_hi = vshll_n_u16(vget_high_u16(vh), 16); 71 72 const uint32x4_t vsign_lo = vandq_u32(vw_lo, vsign_mask); 73 const uint32x4_t vsign_hi = vandq_u32(vw_hi, vsign_mask); 74 75 const uint32x4_t vnonsign_lo = veorq_u32(vw_lo, vsign_lo); 76 const uint32x4_t vnonsign_hi = veorq_u32(vw_hi, vsign_hi); 77 78 const float32x4_t vnorm_lo = vmulq_f32(vreinterpretq_f32_u32(vsraq_n_u32(vexp_offset, vnonsign_lo, 3)), vexp_scale); 79 const float32x4_t vnorm_hi = vmulq_f32(vreinterpretq_f32_u32(vsraq_n_u32(vexp_offset, vnonsign_hi, 3)), vexp_scale); 80 81 const float32x4_t vdenorm_lo = vsubq_f32(vreinterpretq_f32_u32(vsriq_n_u32(vmagic_bias, vnonsign_lo, 16)), vreinterpretq_f32_u32(vmagic_bias)); 82 const float32x4_t vdenorm_hi = vsubq_f32(vreinterpretq_f32_u32(vsriq_n_u32(vmagic_bias, vnonsign_hi, 16)), vreinterpretq_f32_u32(vmagic_bias)); 83 84 const uint32x4_t vxmask_lo = vcgtq_u32(vnonsign_lo, vdenorm_cutoff); 85 const uint32x4_t vf_lo = vorrq_u32(vsign_lo, vreinterpretq_u32_f32(vbslq_f32(vxmask_lo, vnorm_lo, vdenorm_lo))); 86 87 const uint32x4_t vxmask_hi = vcgtq_u32(vnonsign_hi, vdenorm_cutoff); 88 const uint32x4_t vf_hi = vorrq_u32(vsign_hi, vreinterpretq_u32_f32(vbslq_f32(vxmask_hi, vnorm_hi, vdenorm_hi))); 89 90 vst1q_f32(output, vreinterpretq_f32_u32(vf_lo)); output += 4; 91 vst1q_f32(output, vreinterpretq_f32_u32(vf_hi)); output += 4; 92 } 93 if XNN_UNPREDICTABLE(n != 0) { 94 const uint16x8_t vh = vld1q_u16(i); i += 8; 95 96 const uint32x4_t vw_lo = vshll_n_u16(vget_low_u16(vh), 16); 97 const uint32x4_t vw_hi = vshll_n_u16(vget_high_u16(vh), 16); 98 99 const uint32x4_t vsign_lo = vandq_u32(vw_lo, vsign_mask); 100 const uint32x4_t vsign_hi = vandq_u32(vw_hi, vsign_mask); 101 102 const uint32x4_t vnonsign_lo = veorq_u32(vw_lo, vsign_lo); 103 const uint32x4_t vnonsign_hi = veorq_u32(vw_hi, vsign_hi); 104 105 const float32x4_t vnorm_lo = vmulq_f32(vreinterpretq_f32_u32(vsraq_n_u32(vexp_offset, vnonsign_lo, 3)), vexp_scale); 106 const float32x4_t vnorm_hi = vmulq_f32(vreinterpretq_f32_u32(vsraq_n_u32(vexp_offset, vnonsign_hi, 3)), vexp_scale); 107 108 const float32x4_t vdenorm_lo = vsubq_f32(vreinterpretq_f32_u32(vsriq_n_u32(vmagic_bias, vnonsign_lo, 16)), vreinterpretq_f32_u32(vmagic_bias)); 109 const float32x4_t vdenorm_hi = vsubq_f32(vreinterpretq_f32_u32(vsriq_n_u32(vmagic_bias, vnonsign_hi, 16)), vreinterpretq_f32_u32(vmagic_bias)); 110 111 const uint32x4_t vxmask_lo = vcgtq_u32(vnonsign_lo, vdenorm_cutoff); 112 uint32x4_t vf = vorrq_u32(vsign_lo, vreinterpretq_u32_f32(vbslq_f32(vxmask_lo, vnorm_lo, vdenorm_lo))); 113 114 if (n & (4 * sizeof(uint16_t))) { 115 vst1q_f32(output, vreinterpretq_f32_u32(vf)); output += 4; 116 117 const uint32x4_t vxmask_hi = vcgtq_u32(vnonsign_hi, vdenorm_cutoff); 118 vf = vorrq_u32(vsign_hi, vreinterpretq_u32_f32(vbslq_f32(vxmask_hi, vnorm_hi, vdenorm_hi))); 119 } 120 uint32x2_t vf_lo = vget_low_u32(vf); 121 if (n & (2 * sizeof(uint16_t))) { 122 vst1_f32(output, vreinterpret_f32_u32(vf_lo)); output += 2; 123 vf_lo = vget_high_u32(vf); 124 } 125 if (n & (1 * sizeof(uint16_t))) { 126 vst1_lane_f32(output, vreinterpret_f32_u32(vf_lo), 0); 127 } 128 } 129} 130