1 /* 2 * Copyright (c) 2021 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_POOL2D_H 25 #define ARM_COMPUTE_CPU_POOL2D_H 26 27 #include "arm_compute/core/experimental/Types.h" 28 #include "src/core/common/Macros.h" 29 #include "src/cpu/ICpuOperator.h" 30 31 #include <memory> 32 33 namespace arm_compute 34 { 35 // Forward Declarations 36 struct PoolingLayerInfo; 37 38 namespace cpu 39 { 40 /** Basic function to simulate a pooling layer with the specified pooling operation. This function calls the following kernels: 41 * 42 * -# @ref NEFillBorderKernel (executed if padding size is different from zero) 43 * -# @ref kernels::CpuPool2dKernel 44 * -# @ref kernels::CpuPool2dAssemblyWrapperKernel 45 */ 46 class CpuPool2d : public ICpuOperator 47 { 48 public: 49 CpuPool2d(); 50 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuPool2d); 51 ~CpuPool2d(); 52 /** Set the src and dst tensors. 53 * 54 * @note F16 is supported for pool sizes 2 and 3 only 55 * 56 * @param[in, out] src Source tensor info. (Written to only when padding != 0) Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. 57 * @param[out] dst Destination tensor info. Data types supported: same as @p src. 58 * @param[in] pool_info Contains pooling operation information described in @ref PoolingLayerInfo. 59 * @param[out] indices (optional) The indices of the maximal values. Data type supported: U32. 60 */ 61 void configure(ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &pool_info, ITensorInfo *indices = nullptr); 62 /** Static function to check if given info will lead to a valid configuration 63 * 64 * Similar to CpuPool2d::configure() 65 * 66 * @return a status 67 */ 68 static Status validate(const ITensorInfo *src, const ITensorInfo *dst, const PoolingLayerInfo &pool_info, const ITensorInfo *indices = nullptr); 69 70 // Inherited methods overridden: 71 void run(ITensorPack &tensors) override; 72 experimental::MemoryRequirements workspace() const override; 73 74 private: 75 std::unique_ptr<INEKernel> _pooling_layer_kernel; 76 std::unique_ptr<INEKernel> _asm_glue; 77 78 bool _is_global_pooling_layer; 79 DataLayout _data_layout; 80 experimental::MemoryRequirements _aux_mem{}; 81 }; 82 } // namespace cpu 83 } // namespace arm_compute 84 #endif /* ARM_COMPUTE_CPU_POOL2D_H */ 85