1 /* 2 * Copyright (c) 2021 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_DIRECTCONV2D_H 25 #define ARM_COMPUTE_CPU_DIRECTCONV2D_H 26 27 #include "arm_compute/core/ITensorInfo.h" 28 #include "arm_compute/core/Types.h" 29 #include "arm_compute/core/experimental/Types.h" 30 #include "arm_compute/runtime/IMemoryManager.h" 31 #include "arm_compute/runtime/MemoryGroup.h" 32 #include "arm_compute/runtime/NEON/functions/NEActivationLayer.h" 33 #include "arm_compute/runtime/Tensor.h" 34 #include "src/core/NEON/kernels/NEFillBorderKernel.h" 35 #include "src/cpu/ICpuKernel.h" 36 #include "src/cpu/ICpuOperator.h" 37 #include "src/cpu/kernels/CpuDirectConv2dKernel.h" 38 #include "src/cpu/kernels/CpuDirectConv2dOutputStageKernel.h" 39 #include "src/cpu/operators/CpuActivation.h" 40 41 #include <memory> 42 43 namespace arm_compute 44 { 45 namespace cpu 46 { 47 /** Function to run the direct convolution. 48 * 49 * This function calls the following kernels: 50 * 51 * -# @ref NEFillBorderKernel for the input 52 * -# @ref kernels::CpuDirectConv2dOutputStageKernel 53 * -# @ref kernels::CpuDirectConv2dKernel 54 */ 55 class CpuDirectConv2d : public ICpuOperator 56 { 57 public: 58 CpuDirectConv2d(std::shared_ptr<IMemoryManager> memory_manager = nullptr); 59 ~CpuDirectConv2d(); 60 /** Set the input, weights, biases and output tensors. 61 * 62 * @note: DirectConvolution only works in the following configurations: 63 * 1x1 convolution with stride_x = 1/2/3, stride_y = 1/2/3 data type = F16/F32 64 * 3x3 convolution with stride_x = 1/2/3, stride_y = 1/2/3 data type = F16/F32 65 * 5x5 convolution with stride_x = 1/2/3, stride_y = 1/2/3 data type = F32 66 * 67 * @param[in, out] src Input tensor info. Data types supported: F16/F32. 68 * @param[in] weights Set of kernels to convolve the input volume. 69 * Supported sizes: 1x1, 3x3 and 5x5. 70 * The 3rd dimension must be the same as the input's volume 3rd dimension. 71 * Data type supported: Same as @p src. 72 * @param[in] bias Set of biases. Can be nullptr. Data type supported: Same as @p src. 73 * @param[out] dst Output tensor info. 74 * The 3rd dimensions must be equal to the 4th dimension of the @p kernels tensor. Data types supported: Same as @p input. 75 * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo. 76 * @param[in] act_info (Optional) Activation layer information in case of a fused activation. 77 */ 78 void configure(ITensorInfo *src, ITensorInfo *weights, const ITensorInfo *bias, ITensorInfo *dst, const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info = ActivationLayerInfo()); 79 /** Static function to check if given info will lead to a valid configuration 80 * 81 * Similar to CpuDirectConv2d::configure() 82 * 83 * @return a status 84 */ 85 static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *bias, const ITensorInfo *dst, const PadStrideInfo &conv_info, 86 const ActivationLayerInfo &act_info = ActivationLayerInfo()); 87 88 // Inherited methods overridden: 89 void run(ITensorPack &tensors) override; 90 91 private: 92 MemoryGroup _memory_group; 93 std::unique_ptr<kernels::CpuDirectConv2dOutputStageKernel> _output_stage_kernel; 94 std::unique_ptr<kernels::CpuDirectConv2dKernel> _conv_kernel; 95 std::unique_ptr<NEFillBorderKernel> _input_border_handler; 96 std::unique_ptr<CpuActivation> _activationlayer_function; 97 Tensor _accumulator; 98 bool _has_bias{ false }; 99 bool _is_activationlayer_enabled{ false }; 100 unsigned int _dim_split{ 0 }; 101 bool _is_padding_required{ false }; 102 }; 103 } // namespace cpu 104 } // namespace arm_compute 105 #endif /* ARM_COMPUTE_CPU_DIRECTCONV2D_H */ 106