1 /* 2 * Copyright (c) 2019-2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_ASSEMBLY_WRAPPER_KERNEL_H 25 #define ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_ASSEMBLY_WRAPPER_KERNEL_H 26 27 #include "arm_compute/core/Types.h" 28 #include "src/core/common/Macros.h" 29 #include "src/cpu/ICpuKernel.h" 30 #include "src/cpu/kernels/CpuKernelSelectionTypes.h" 31 32 namespace arm_conv 33 { 34 namespace depthwise 35 { 36 // Forward declarations 37 class IDepthwiseCommon; 38 } // depthwise 39 } // arm_conv 40 41 namespace arm_compute 42 { 43 namespace cpu 44 { 45 namespace kernels 46 { 47 /** This class is a wrapper for the depthwise convolution assembly kernels. */ 48 class CpuDepthwiseConv2dAssemblyWrapperKernel final : public ICpuKernel<CpuDepthwiseConv2dAssemblyWrapperKernel> 49 { 50 public: 51 /** Default constructor */ 52 CpuDepthwiseConv2dAssemblyWrapperKernel(); 53 ~CpuDepthwiseConv2dAssemblyWrapperKernel(); 54 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuDepthwiseConv2dAssemblyWrapperKernel); 55 56 /** Initialise the kernel's src and dst. 57 * 58 * @param[in] src Source tensor info. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. 59 * @param[in] weights Weights tensor info. These are 3D tensors with shape [kernel_x, kernel_y, IFM]. 60 * Data type supported: same as @p src or QASYMM8/QASYMM8_SIGNED/QSYMM8_PER_CHANNEL when @p src is QASYMM8/QASYMM8_SIGNED. 61 * @param[in] bias Bias tensor. A 1D tensor with shape [IFM]. Must be nullptr if not needed. 62 * Data type supported: same as @p src, S32 when @p src is QASYMM8/QASYMM8_SIGNED. 63 * @param[out] dst Destination tensor info. Data type supported: same as @p input. 64 * @param[in] info Depthwise convolution layer meta-data. 65 * @param[in] cpu_info CPU information needed to select the most appropriate kernel. 66 */ 67 void configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *bias, ITensorInfo *dst, const ConvolutionInfo &info, const CPUInfo &cpu_info); 68 69 /** Indicates whether or not this function can be used to process the given parameters. 70 * 71 * Similar to @ref CpuDepthwiseConv2dAssemblyWrapperKernel::configure() 72 * 73 * @return a status. 74 */ 75 static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *bias, const ITensorInfo *dst, const ConvolutionInfo &info); 76 77 // Inherited methods overridden: 78 void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override; 79 const char *name() const override; 80 81 /** Pack bias and weights in a storage space for the assembly kernel 82 * 83 * @param[in] parameters_ptr Pointer to storage space. 84 * @param[in] bias_ptr Pointer to bias buffer. 85 * @param[in] weights_ptr Pointer to weights buffer. 86 * @param[in] ld_weights_col Columns displacement for the weights tensor. 87 * @param[in] ld_weights_row Rows displacement for the weights tensor. 88 */ 89 void pack_parameters(void *parameters_ptr, void *bias_ptr, void *weights_ptr, size_t ld_weights_col, size_t ld_weights_row); 90 91 /** Get the amount of storage space required for the rearranged weights and bias. 92 * 93 * @return size of workspace 94 */ 95 size_t get_storage_size() const; 96 97 /** Get size of the workspace needed by the assembly kernel. 98 * 99 * @param[in] num_threads Maximum number of threads that are going to be spawned. 100 * @param[in] num_input_channels Number of channels of the input tensor. 101 * 102 * @return size of workspace 103 */ 104 size_t get_working_size(unsigned int num_threads, unsigned int num_input_channels) const; 105 106 /** Was the asm kernel successfully configured? 107 * 108 * @return True if the asm kernel is configured and ready to run 109 */ 110 bool is_configured() const; 111 112 /** Return minimum workload size of the relevant kernel 113 * 114 * @param[in] platform The CPU platform used to create the context. 115 * @param[in] thread_count Number of threads in the execution. 116 * 117 * @return[out] small_network_mws Minimum workload size for requsted configuration. 118 */ 119 size_t get_mws(const CPUInfo &platform, size_t thread_count) const override; 120 121 private: 122 std::unique_ptr<arm_conv::depthwise::IDepthwiseCommon> _kernel_asm; 123 std::vector<int32_t> _multipliers{}; 124 std::vector<int32_t> _left_shifts{}; 125 std::vector<int32_t> _right_shifts{}; 126 std::string _name{}; 127 }; 128 } // namespace kernels 129 } // namespace cpu 130 } // namespace arm_compute 131 #endif /* ARM_COMPUTE_CPU_DEPTHWISE_CONV2D_ASSEMBLY_WRAPPER_KERNEL_H */ 132