1 /*
2  * Copyright (c) 2022 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to
8  * deal in the Software without restriction, including without limitation the
9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10  * sell copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in all
14  * copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 
25 #if defined(ARM_COMPUTE_ENABLE_SME)
26 
27 #include <cstddef>
28 
29 namespace arm_conv {
30 namespace winograd {
31 namespace input_transform {
32 
sme_fp32_mla_6x6(const unsigned int num_channels,const float * input,const size_t input_row_stride,const size_t input_col_stride,float * output,const size_t output_col_stride)33 void sme_fp32_mla_6x6(
34   const unsigned int num_channels,
35   const float *input,
36   const size_t input_row_stride,
37   const size_t input_col_stride,
38   float *output,
39   const size_t output_col_stride
40 )
41 {
42   const float B_values[4] = { 1.0f, 2.0f, 4.0f, 5.0f };
43   long long_channels = num_channels;
44 
45   // Generated by armasmgen (February 04th, 2021)
46   __asm__ __volatile__(
47       ".inst 0xd503477f  // SMSTART ZA\n"
48       "fmov z16.s, #4.0\n"
49       "ptrue p1.b\n"
50       "ld1rqw { z2.s }, p1/Z, [%x[B_values]]\n"
51       "add x16, %x[input_row_0], %x[input_row_stride], LSL #2\n"
52       "add x15, %x[output_row_0], %x[output_row_stride], LSL #2\n"
53       "add x14, %x[input_row_0], %x[input_row_stride], LSL #3\n"
54       "add x13, %x[output_row_0], %x[output_row_stride], LSL #3\n"
55       "add x12, x14, %x[input_row_stride], LSL #2\n"
56       "add x11, x13, %x[output_row_stride], LSL #2\n"
57       "add x10, %x[input_row_0], %x[input_row_stride], LSL #4\n"
58       "add x9, %x[output_row_0], %x[output_row_stride], LSL #4\n"
59       "add x28, x10, %x[input_row_stride], LSL #2\n"
60       "add x27, x9, %x[output_row_stride], LSL #2\n"
61       "lsl x26, %x[input_col_1_stride], #0x1\n"
62       "lsl x25, %x[output_col_1_stride], #0x1\n"
63       "add x24, x26, %x[input_col_1_stride]\n"
64       "add x23, x25, %x[output_col_1_stride]\n"
65       "lsl x22, %x[input_col_1_stride], #0x2\n"
66       "lsl x21, %x[output_col_1_stride], #0x2\n"
67       "add x20, x22, %x[input_col_1_stride]\n"
68       "add x19, x21, %x[output_col_1_stride]\n"
69       "whilelt p0.s, XZR, %x[num_channels]\n"
70       "beq 2f\n"
71       "1:"  // channel_loop
72       "ld1w { z31.s }, p0/Z, [%x[input_row_0]]\n"
73       "decw %x[num_channels]\n"
74       "ld1w { z28.s }, p0/Z, [%x[input_row_0], %x[input_col_1_stride], LSL #2]\n"
75       "fmul z13.s, z28.s, z2.s[1]\n"
76       "ld1w { z27.s }, p0/Z, [%x[input_row_0], x26, LSL #2]\n"
77       "ld1w { z11.s }, p0/Z, [%x[input_row_0], x24, LSL #2]\n"
78       "fneg z13.s, p1/M, z13.s\n"
79       "ld1w { z7.s }, p0/Z, [%x[input_row_0], x22, LSL #2]\n"
80       "fsub z15.s, z7.s, z27.s\n"
81       "fmad z31.s, p1/M, z16.s, z7.s\n"
82       "ld1w { z3.s }, p0/Z, [%x[input_row_0], x20, LSL #2]\n"
83       "fmla z13.s, z11.s, z2.s[1]\n"
84       "ld1w { z12.s }, p0/Z, [x14]\n"
85       "incb %x[input_row_0]\n"
86       "fmls z31.s, z27.s, z2.s[3]\n"
87       "ld1w { z14.s }, p0/Z, [x14, %x[input_col_1_stride], LSL #2]\n"
88       "fsub z25.s, z15.s, z13.s\n"
89       "fadd z8.s, z13.s, z15.s\n"
90       "ld1w { z24.s }, p0/Z, [x14, x26, LSL #2]\n"
91       "fmsb z27.s, p1/M, z16.s, z7.s\n"
92       "ld1w { z22.s }, p0/Z, [x14, x24, LSL #2]\n"
93       "fmul z7.s, z28.s, z2.s[2]\n"
94       "ld1w { z1.s }, p0/Z, [x14, x22, LSL #2]\n"
95       "fsub z15.s, z1.s, z24.s\n"
96       "fneg z7.s, p1/M, z7.s\n"
97       "ld1w { z20.s }, p0/Z, [x14, x20, LSL #2]\n"
98       "fadd z7.s, z7.s, z11.s\n"
99       "ld1w { z29.s }, p0/Z, [x10]\n"
100       "incb x14\n"
101       "fmad z28.s, p1/M, z16.s, z3.s\n"
102       "ld1w { z10.s }, p0/Z, [x10, %x[input_col_1_stride], LSL #2]\n"
103       "fmad z12.s, p1/M, z16.s, z1.s\n"
104       "ld1w { z18.s }, p0/Z, [x10, x26, LSL #2]\n"
105       "fmul z13.s, z14.s, z2.s[1]\n"
106       "ld1w { z19.s }, p0/Z, [x10, x24, LSL #2]\n"
107       "fadd z17.s, z7.s, z27.s\n"
108       "ld1w { z9.s }, p0/Z, [x10, x22, LSL #2]\n"
109       "fsub z27.s, z27.s, z7.s\n"
110       "fmls z28.s, z11.s, z2.s[3]\n"
111       "ld1w { z21.s }, p0/Z, [x10, x20, LSL #2]\n"
112       "incb x10\n"
113       "fmls z12.s, z24.s, z2.s[3]\n"
114       "fneg z13.s, p1/M, z13.s\n"
115       "fmla z13.s, z22.s, z2.s[1]\n"
116       "fsub z30.s, z15.s, z13.s\n"
117       "fadd z4.s, z13.s, z15.s\n"
118       "fmsb z24.s, p1/M, z16.s, z1.s\n"
119       "fsub z15.s, z9.s, z18.s\n"
120       "fmul z1.s, z14.s, z2.s[2]\n"
121       "fmad z14.s, p1/M, z16.s, z20.s\n"
122       "fmad z29.s, p1/M, z16.s, z9.s\n"
123       "fmul z13.s, z10.s, z2.s[1]\n"
124       "fneg z1.s, p1/M, z1.s\n"
125       "fadd z1.s, z1.s, z22.s\n"
126       "fmls z14.s, z22.s, z2.s[3]\n"
127       "fmls z29.s, z18.s, z2.s[3]\n"
128       "fadd z5.s, z1.s, z24.s\n"
129       "fsub z24.s, z24.s, z1.s\n"
130       "fneg z13.s, p1/M, z13.s\n"
131       "fmla z13.s, z19.s, z2.s[1]\n"
132       "fsub z23.s, z15.s, z13.s\n"
133       "fadd z11.s, z13.s, z15.s\n"
134       "fmsb z18.s, p1/M, z16.s, z9.s\n"
135       "fmul z9.s, z10.s, z2.s[2]\n"
136       "fmad z10.s, p1/M, z16.s, z21.s\n"
137       "fmad z31.s, p1/M, z16.s, z29.s\n"
138       "fmad z8.s, p1/M, z16.s, z11.s\n"
139       "fneg z9.s, p1/M, z9.s\n"
140       "fadd z9.s, z9.s, z19.s\n"
141       "fmls z10.s, z19.s, z2.s[3]\n"
142       "fmls z31.s, z12.s, z2.s[3]\n"
143       "st1w { z31.s }, p0, [%x[output_row_0]]\n"
144       "fadd z26.s, z9.s, z18.s\n"
145       "fsub z18.s, z18.s, z9.s\n"
146       "fmls z8.s, z4.s, z2.s[3]\n"
147       "fmad z25.s, p1/M, z16.s, z23.s\n"
148       "fmad z28.s, p1/M, z16.s, z10.s\n"
149       "fmad z17.s, p1/M, z16.s, z26.s\n"
150       "fmad z27.s, p1/M, z16.s, z18.s\n"
151       "fmls z25.s, z30.s, z2.s[3]\n"
152       "fmls z28.s, z14.s, z2.s[3]\n"
153       "fmls z17.s, z5.s, z2.s[3]\n"
154       "st1w { z17.s }, p0, [%x[output_row_0], %x[output_col_1_stride], LSL #2]\n"
155       "fmls z27.s, z24.s, z2.s[3]\n"
156       "st1w { z27.s }, p0, [%x[output_row_0], x25, LSL #2]\n"
157       "st1w { z8.s }, p0, [%x[output_row_0], x23, LSL #2]\n"
158       "st1w { z25.s }, p0, [%x[output_row_0], x21, LSL #2]\n"
159       "st1w { z28.s }, p0, [%x[output_row_0], x19, LSL #2]\n"
160       "incb %x[output_row_0]\n"
161       "ld1w { z19.s }, p0/Z, [x16]\n"
162       "ld1w { z7.s }, p0/Z, [x16, %x[input_col_1_stride], LSL #2]\n"
163       "fmul z13.s, z7.s, z2.s[1]\n"
164       "ld1w { z6.s }, p0/Z, [x16, x26, LSL #2]\n"
165       "ld1w { z27.s }, p0/Z, [x16, x24, LSL #2]\n"
166       "fneg z13.s, p1/M, z13.s\n"
167       "ld1w { z25.s }, p0/Z, [x16, x22, LSL #2]\n"
168       "fsub z15.s, z25.s, z6.s\n"
169       "fmad z19.s, p1/M, z16.s, z25.s\n"
170       "ld1w { z20.s }, p0/Z, [x16, x20, LSL #2]\n"
171       "fmla z13.s, z27.s, z2.s[1]\n"
172       "ld1w { z0.s }, p0/Z, [x12]\n"
173       "incb x16\n"
174       "fmls z19.s, z6.s, z2.s[3]\n"
175       "ld1w { z31.s }, p0/Z, [x12, %x[input_col_1_stride], LSL #2]\n"
176       "fsub z8.s, z15.s, z13.s\n"
177       "fadd z28.s, z13.s, z15.s\n"
178       "ld1w { z1.s }, p0/Z, [x12, x26, LSL #2]\n"
179       "fmsb z6.s, p1/M, z16.s, z25.s\n"
180       "ld1w { z21.s }, p0/Z, [x12, x24, LSL #2]\n"
181       "fmul z25.s, z7.s, z2.s[2]\n"
182       "ld1w { z22.s }, p0/Z, [x12, x22, LSL #2]\n"
183       "fsub z15.s, z22.s, z1.s\n"
184       "fneg z25.s, p1/M, z25.s\n"
185       "ld1w { z17.s }, p0/Z, [x12, x20, LSL #2]\n"
186       "fadd z25.s, z25.s, z27.s\n"
187       "incb x12\n"
188       "fmad z7.s, p1/M, z16.s, z20.s\n"
189       "fmad z0.s, p1/M, z16.s, z22.s\n"
190       "fmul z13.s, z31.s, z2.s[1]\n"
191       "fadd z3.s, z25.s, z6.s\n"
192       "fsub z6.s, z6.s, z25.s\n"
193       "fmls z7.s, z27.s, z2.s[3]\n"
194       "fmls z0.s, z1.s, z2.s[3]\n"
195       "fneg z13.s, p1/M, z13.s\n"
196       "fmla z13.s, z21.s, z2.s[1]\n"
197       "fsub z9.s, z15.s, z13.s\n"
198       "fadd z27.s, z13.s, z15.s\n"
199       "fmsb z1.s, p1/M, z16.s, z22.s\n"
200       "fsub z15.s, z29.s, z12.s\n"
201       "fmul z22.s, z31.s, z2.s[2]\n"
202       "fmad z31.s, p1/M, z16.s, z17.s\n"
203       "fmul z13.s, z19.s, z2.s[1]\n"
204       "fmsb z12.s, p1/M, z16.s, z29.s\n"
205       "fneg z22.s, p1/M, z22.s\n"
206       "fadd z22.s, z22.s, z21.s\n"
207       "fmls z31.s, z21.s, z2.s[3]\n"
208       "fneg z13.s, p1/M, z13.s\n"
209       "fadd z25.s, z22.s, z1.s\n"
210       "fsub z1.s, z1.s, z22.s\n"
211       "fmla z13.s, z0.s, z2.s[1]\n"
212       "fmul z29.s, z19.s, z2.s[2]\n"
213       "fadd z22.s, z13.s, z15.s\n"
214       "st1w { z22.s }, p0, [x11]\n"
215       "fneg z29.s, p1/M, z29.s\n"
216       "fsub z22.s, z15.s, z13.s\n"
217       "fadd z29.s, z29.s, z0.s\n"
218       "st1w { z22.s }, p0, [x9]\n"
219       "fadd z22.s, z29.s, z12.s\n"
220       "fsub z15.s, z26.s, z5.s\n"
221       "fmul z13.s, z3.s, z2.s[1]\n"
222       "fsub z12.s, z12.s, z29.s\n"
223       "fmsb z5.s, p1/M, z16.s, z26.s\n"
224       "fmul z26.s, z3.s, z2.s[2]\n"
225       "fneg z13.s, p1/M, z13.s\n"
226       "fmla z13.s, z25.s, z2.s[1]\n"
227       "fneg z26.s, p1/M, z26.s\n"
228       "fadd z26.s, z26.s, z25.s\n"
229       "fadd z21.s, z13.s, z15.s\n"
230       "st1w { z21.s }, p0, [x11, %x[output_col_1_stride], LSL #2]\n"
231       "fsub z21.s, z15.s, z13.s\n"
232       "fmul z13.s, z6.s, z2.s[1]\n"
233       "fneg z13.s, p1/M, z13.s\n"
234       "st1w { z21.s }, p0, [x9, %x[output_col_1_stride], LSL #2]\n"
235       "fadd z21.s, z26.s, z5.s\n"
236       "fsub z15.s, z18.s, z24.s\n"
237       "fmla z13.s, z1.s, z2.s[1]\n"
238       "fsub z5.s, z5.s, z26.s\n"
239       "fmsb z24.s, p1/M, z16.s, z18.s\n"
240       "fmul z18.s, z6.s, z2.s[2]\n"
241       "fadd z20.s, z13.s, z15.s\n"
242       "st1w { z20.s }, p0, [x11, x25, LSL #2]\n"
243       "fneg z18.s, p1/M, z18.s\n"
244       "fsub z20.s, z15.s, z13.s\n"
245       "fadd z18.s, z18.s, z1.s\n"
246       "st1w { z20.s }, p0, [x9, x25, LSL #2]\n"
247       "fadd z20.s, z18.s, z24.s\n"
248       "fsub z15.s, z11.s, z4.s\n"
249       "fmul z13.s, z28.s, z2.s[1]\n"
250       "fsub z24.s, z24.s, z18.s\n"
251       "fmsb z4.s, p1/M, z16.s, z11.s\n"
252       "fmul z11.s, z28.s, z2.s[2]\n"
253       "fneg z13.s, p1/M, z13.s\n"
254       "fmla z13.s, z27.s, z2.s[1]\n"
255       "fneg z11.s, p1/M, z11.s\n"
256       "fadd z11.s, z11.s, z27.s\n"
257       "fadd z26.s, z13.s, z15.s\n"
258       "st1w { z26.s }, p0, [x11, x23, LSL #2]\n"
259       "fsub z26.s, z15.s, z13.s\n"
260       "fmul z13.s, z8.s, z2.s[1]\n"
261       "fneg z13.s, p1/M, z13.s\n"
262       "st1w { z26.s }, p0, [x9, x23, LSL #2]\n"
263       "fadd z26.s, z11.s, z4.s\n"
264       "fsub z15.s, z23.s, z30.s\n"
265       "fmla z13.s, z9.s, z2.s[1]\n"
266       "fsub z4.s, z4.s, z11.s\n"
267       "fmsb z30.s, p1/M, z16.s, z23.s\n"
268       "fmul z23.s, z8.s, z2.s[2]\n"
269       "fadd z18.s, z13.s, z15.s\n"
270       "st1w { z18.s }, p0, [x11, x21, LSL #2]\n"
271       "fneg z23.s, p1/M, z23.s\n"
272       "fsub z18.s, z15.s, z13.s\n"
273       "fadd z23.s, z23.s, z9.s\n"
274       "st1w { z18.s }, p0, [x9, x21, LSL #2]\n"
275       "fadd z18.s, z23.s, z30.s\n"
276       "fsub z15.s, z10.s, z14.s\n"
277       "fmul z13.s, z7.s, z2.s[1]\n"
278       "fsub z30.s, z30.s, z23.s\n"
279       "fmsb z14.s, p1/M, z16.s, z10.s\n"
280       "fmul z10.s, z7.s, z2.s[2]\n"
281       "fneg z13.s, p1/M, z13.s\n"
282       "fmla z13.s, z31.s, z2.s[1]\n"
283       "fneg z10.s, p1/M, z10.s\n"
284       "fadd z10.s, z10.s, z31.s\n"
285       "fadd z17.s, z13.s, z15.s\n"
286       "st1w { z17.s }, p0, [x11, x19, LSL #2]\n"
287       "fsub z17.s, z15.s, z13.s\n"
288       "incb x11\n"
289       "st1w { z17.s }, p0, [x9, x19, LSL #2]\n"
290       "fadd z17.s, z10.s, z14.s\n"
291       "fsub z14.s, z14.s, z10.s\n"
292       "st1w { z22.s }, p0, [x15]\n"
293       "incb x9\n"
294       "st1w { z12.s }, p0, [x13]\n"
295       "st1w { z21.s }, p0, [x15, %x[output_col_1_stride], LSL #2]\n"
296       "st1w { z5.s }, p0, [x13, %x[output_col_1_stride], LSL #2]\n"
297       "st1w { z20.s }, p0, [x15, x25, LSL #2]\n"
298       "st1w { z24.s }, p0, [x13, x25, LSL #2]\n"
299       "st1w { z26.s }, p0, [x15, x23, LSL #2]\n"
300       "st1w { z4.s }, p0, [x13, x23, LSL #2]\n"
301       "st1w { z18.s }, p0, [x15, x21, LSL #2]\n"
302       "st1w { z30.s }, p0, [x13, x21, LSL #2]\n"
303       "st1w { z17.s }, p0, [x15, x19, LSL #2]\n"
304       "incb x15\n"
305       "st1w { z14.s }, p0, [x13, x19, LSL #2]\n"
306       "incb x13\n"
307       "ld1w { z23.s }, p0/Z, [x28]\n"
308       "ld1w { z22.s }, p0/Z, [x28, %x[input_col_1_stride], LSL #2]\n"
309       "fmul z13.s, z22.s, z2.s[1]\n"
310       "ld1w { z21.s }, p0/Z, [x28, x26, LSL #2]\n"
311       "ld1w { z20.s }, p0/Z, [x28, x24, LSL #2]\n"
312       "fneg z13.s, p1/M, z13.s\n"
313       "ld1w { z26.s }, p0/Z, [x28, x22, LSL #2]\n"
314       "fsub z15.s, z26.s, z21.s\n"
315       "fmad z23.s, p1/M, z16.s, z26.s\n"
316       "ld1w { z18.s }, p0/Z, [x28, x20, LSL #2]\n"
317       "fmla z13.s, z20.s, z2.s[1]\n"
318       "incb x28\n"
319       "fmls z23.s, z21.s, z2.s[3]\n"
320       "fsub z17.s, z15.s, z13.s\n"
321       "fadd z30.s, z13.s, z15.s\n"
322       "fmsb z21.s, p1/M, z16.s, z26.s\n"
323       "fmul z26.s, z22.s, z2.s[2]\n"
324       "fmad z22.s, p1/M, z16.s, z18.s\n"
325       "fmad z19.s, p1/M, z16.s, z23.s\n"
326       "fmad z28.s, p1/M, z16.s, z30.s\n"
327       "fneg z26.s, p1/M, z26.s\n"
328       "fadd z26.s, z26.s, z20.s\n"
329       "fmls z22.s, z20.s, z2.s[3]\n"
330       "fmls z19.s, z0.s, z2.s[3]\n"
331       "st1w { z19.s }, p0, [x27]\n"
332       "fadd z23.s, z26.s, z21.s\n"
333       "fsub z21.s, z21.s, z26.s\n"
334       "fmls z28.s, z27.s, z2.s[3]\n"
335       "fmad z8.s, p1/M, z16.s, z17.s\n"
336       "fmad z7.s, p1/M, z16.s, z22.s\n"
337       "fmad z3.s, p1/M, z16.s, z23.s\n"
338       "fmad z6.s, p1/M, z16.s, z21.s\n"
339       "fmls z8.s, z9.s, z2.s[3]\n"
340       "fmls z7.s, z31.s, z2.s[3]\n"
341       "fmls z3.s, z25.s, z2.s[3]\n"
342       "st1w { z3.s }, p0, [x27, %x[output_col_1_stride], LSL #2]\n"
343       "fmls z6.s, z1.s, z2.s[3]\n"
344       "st1w { z6.s }, p0, [x27, x25, LSL #2]\n"
345       "st1w { z28.s }, p0, [x27, x23, LSL #2]\n"
346       "st1w { z8.s }, p0, [x27, x21, LSL #2]\n"
347       "st1w { z7.s }, p0, [x27, x19, LSL #2]\n"
348       "incb x27\n"
349       "whilelt p0.s, XZR, %x[num_channels]\n"
350       "bne 1b\n"
351       "2:"  // channel_loop_end
352       ".inst 0xd503467f  // SMSTOP\n"
353       : [input_row_0] "+&r" (input), [num_channels] "+&r" (long_channels), [output_row_0] "+&r" (output)
354       : [B_values] "r" (B_values), [input_col_1_stride] "r" ((long) input_col_stride), [input_row_stride] "r" ((long) input_row_stride), [output_col_1_stride] "r" ((long) output_col_stride), [output_row_stride] "r" (6 * (long) output_col_stride)
355       : "cc", "memory", "p0", "p1", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31"
356   );
357 }
358 
359 }  // namespace input_transform
360 }  // namespace winograd
361 }  // namespace arm_conv
362 
363 #endif  // defined(ARM_COMPUTE_ENABLE_SME)
364