1 // Headers from LSDp CL1744173 2 #ifndef _vpe_6_1_0_SH_MASK_HEADER 3 #define _vpe_6_1_0_SH_MASK_HEADER 4 5 6 // addressBlock: vpe_vpedec 7 //VPEC_DEC_START 8 #define VPEC_DEC_START__START__SHIFT 0x0 9 #define VPEC_DEC_START__START_MASK 0xFFFFFFFFL 10 //VPEC_UCODE_ADDR 11 #define VPEC_UCODE_ADDR__VALUE__SHIFT 0x0 12 #define VPEC_UCODE_ADDR__THID__SHIFT 0xf 13 #define VPEC_UCODE_ADDR__VALUE_MASK 0x00001FFFL 14 #define VPEC_UCODE_ADDR__THID_MASK 0x00008000L 15 //VPEC_UCODE_DATA 16 #define VPEC_UCODE_DATA__VALUE__SHIFT 0x0 17 #define VPEC_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 18 //VPEC_F32_CNTL 19 #define VPEC_F32_CNTL__HALT__SHIFT 0x0 20 #define VPEC_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 21 #define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 22 #define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x9 23 #define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0xa 24 #define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc 25 #define VPEC_F32_CNTL__TH1_RESET__SHIFT 0xd 26 #define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0xe 27 #define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 28 #define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 29 #define VPEC_F32_CNTL__HALT_MASK 0x00000001L 30 #define VPEC_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL 31 #define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L 32 #define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200L 33 #define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400L 34 #define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L 35 #define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000L 36 #define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000L 37 #define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L 38 #define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L 39 //VPEC_MMHUB_CNTL 40 #define VPEC_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 41 #define VPEC_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 42 //VPEC_MMHUB_TRUSTLVL 43 #define VPEC_MMHUB_TRUSTLVL__SECLVL0__SHIFT 0x0 44 #define VPEC_MMHUB_TRUSTLVL__SECLVL1__SHIFT 0x4 45 #define VPEC_MMHUB_TRUSTLVL__SECLVL2__SHIFT 0x8 46 #define VPEC_MMHUB_TRUSTLVL__SECLVL3__SHIFT 0xc 47 #define VPEC_MMHUB_TRUSTLVL__SECLVL4__SHIFT 0x10 48 #define VPEC_MMHUB_TRUSTLVL__SECLVL5__SHIFT 0x14 49 #define VPEC_MMHUB_TRUSTLVL__SECLVL6__SHIFT 0x18 50 #define VPEC_MMHUB_TRUSTLVL__SECLVL7__SHIFT 0x1c 51 #define VPEC_MMHUB_TRUSTLVL__SECLVL0_MASK 0x0000000FL 52 #define VPEC_MMHUB_TRUSTLVL__SECLVL1_MASK 0x000000F0L 53 #define VPEC_MMHUB_TRUSTLVL__SECLVL2_MASK 0x00000F00L 54 #define VPEC_MMHUB_TRUSTLVL__SECLVL3_MASK 0x0000F000L 55 #define VPEC_MMHUB_TRUSTLVL__SECLVL4_MASK 0x000F0000L 56 #define VPEC_MMHUB_TRUSTLVL__SECLVL5_MASK 0x00F00000L 57 #define VPEC_MMHUB_TRUSTLVL__SECLVL6_MASK 0x0F000000L 58 #define VPEC_MMHUB_TRUSTLVL__SECLVL7_MASK 0xF0000000L 59 //VPEC_VPEP_CTRL 60 #define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x0 61 #define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x1 62 #define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x2 63 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x1e 64 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x1f 65 #define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001L 66 #define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002L 67 #define VPEC_VPEP_CTRL__RESERVED_MASK 0x3FFFFFFCL 68 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000L 69 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000L 70 //VPEC_CLK_CTRL 71 #define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x1 72 #define VPEC_CLK_CTRL__RESERVED__SHIFT 0x2 73 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x18 74 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x19 75 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT 0x1a 76 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT 0x1b 77 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT 0x1c 78 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT 0x1d 79 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT 0x1e 80 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT 0x1f 81 #define VPEC_CLK_CTRL__VPECLK_EN_MASK 0x00000002L 82 #define VPEC_CLK_CTRL__RESERVED_MASK 0x00FFFFFCL 83 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK 0x01000000L 84 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK 0x02000000L 85 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK 0x04000000L 86 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK 0x08000000L 87 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK 0x10000000L 88 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK 0x20000000L 89 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK 0x40000000L 90 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK 0x80000000L 91 //VPEC_PG_CNTL 92 #define VPEC_PG_CNTL__PG_EN__SHIFT 0x0 93 #define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT 0x1 94 #define VPEC_PG_CNTL__PG_EN_MASK 0x00000001L 95 #define VPEC_PG_CNTL__PG_HYSTERESIS_MASK 0x0000003EL 96 //VPEC_POWER_CNTL 97 #define VPEC_POWER_CNTL__LS_ENABLE__SHIFT 0x8 98 #define VPEC_POWER_CNTL__LS_ENABLE_MASK 0x00000100L 99 //VPEC_CNTL 100 #define VPEC_CNTL__TRAP_ENABLE__SHIFT 0x0 101 #define VPEC_CNTL__RESERVED_2_2__SHIFT 0x2 102 #define VPEC_CNTL__DATA_SWAP__SHIFT 0x3 103 #define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x5 104 #define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x6 105 #define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 106 #define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 107 #define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT 0xa 108 #define VPEC_CNTL__RESERVED_13_11__SHIFT 0xb 109 #define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe 110 #define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xf 111 #define VPEC_CNTL__RESERVED_16_16__SHIFT 0x10 112 #define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 113 #define VPEC_CNTL__RESERVED_19_19__SHIFT 0x13 114 #define VPEC_CNTL__ZSTATES_ENABLE__SHIFT 0x14 115 #define VPEC_CNTL__ZSTATES_HYSTERESIS__SHIFT 0x15 116 #define VPEC_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 117 #define VPEC_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 118 #define VPEC_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 119 #define VPEC_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f 120 #define VPEC_CNTL__TRAP_ENABLE_MASK 0x00000001L 121 #define VPEC_CNTL__RESERVED_2_2_MASK 0x00000004L 122 #define VPEC_CNTL__DATA_SWAP_MASK 0x00000018L 123 #define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000020L 124 #define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000040L 125 #define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L 126 #define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L 127 #define VPEC_CNTL__UMSCH_INT_ENABLE_MASK 0x00000400L 128 #define VPEC_CNTL__RESERVED_13_11_MASK 0x00003800L 129 #define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000L 130 #define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00008000L 131 #define VPEC_CNTL__RESERVED_16_16_MASK 0x00010000L 132 #define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 133 #define VPEC_CNTL__RESERVED_19_19_MASK 0x00080000L 134 #define VPEC_CNTL__ZSTATES_ENABLE_MASK 0x00100000L 135 #define VPEC_CNTL__ZSTATES_HYSTERESIS_MASK 0x03E00000L 136 #define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 137 #define VPEC_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 138 #define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 139 #define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L 140 //VPEC_CNTL1 141 #define VPEC_CNTL1__RESERVED_3_1__SHIFT 0x1 142 #define VPEC_CNTL1__SRBM_POLL_RETRYING__SHIFT 0x5 143 #define VPEC_CNTL1__RESERVED_23_10__SHIFT 0xa 144 #define VPEC_CNTL1__CG_STATUS_OUTPUT__SHIFT 0x18 145 #define VPEC_CNTL1__SW_FREEZE_ENABLE__SHIFT 0x19 146 #define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE__SHIFT 0x1a 147 #define VPEC_CNTL1__RESERVED__SHIFT 0x1b 148 #define VPEC_CNTL1__RESERVED_3_1_MASK 0x0000000EL 149 #define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK 0x00000020L 150 #define VPEC_CNTL1__RESERVED_23_10_MASK 0x00FFFC00L 151 #define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK 0x01000000L 152 #define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK 0x02000000L 153 #define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK 0x04000000L 154 #define VPEC_CNTL1__RESERVED_MASK 0xF8000000L 155 //VPEC_CNTL2 156 #define VPEC_CNTL2__F32_CMD_PROC_DELAY__SHIFT 0x0 157 #define VPEC_CNTL2__F32_SEND_POSTCODE_EN__SHIFT 0x4 158 #define VPEC_CNTL2__UCODE_BUF_DS_EN__SHIFT 0x6 159 #define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 160 #define VPEC_CNTL2__RESERVED_11_8__SHIFT 0x8 161 #define VPEC_CNTL2__RESERVED_14_12__SHIFT 0xc 162 #define VPEC_CNTL2__RESERVED_15__SHIFT 0xf 163 #define VPEC_CNTL2__RB_FIFO_WATERMARK__SHIFT 0x10 164 #define VPEC_CNTL2__IB_FIFO_WATERMARK__SHIFT 0x12 165 #define VPEC_CNTL2__RESERVED_22_20__SHIFT 0x14 166 #define VPEC_CNTL2__CH_RD_WATERMARK__SHIFT 0x17 167 #define VPEC_CNTL2__CH_WR_WATERMARK__SHIFT 0x19 168 #define VPEC_CNTL2__CH_WR_WATERMARK_LSB__SHIFT 0x1e 169 #define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 170 #define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 171 #define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK 0x00000040L 172 #define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L 173 #define VPEC_CNTL2__RESERVED_11_8_MASK 0x00000F00L 174 #define VPEC_CNTL2__RESERVED_14_12_MASK 0x00007000L 175 #define VPEC_CNTL2__RESERVED_15_MASK 0x00008000L 176 #define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK 0x00030000L 177 #define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK 0x000C0000L 178 #define VPEC_CNTL2__RESERVED_22_20_MASK 0x00700000L 179 #define VPEC_CNTL2__CH_RD_WATERMARK_MASK 0x01800000L 180 #define VPEC_CNTL2__CH_WR_WATERMARK_MASK 0x3E000000L 181 #define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK 0x40000000L 182 //VPEC_GB_ADDR_CONFIG 183 #define VPEC_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 184 #define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 185 #define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 186 #define VPEC_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 187 #define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 188 #define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 189 #define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 190 #define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 191 #define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 192 #define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 193 #define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 194 #define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 195 //VPEC_GB_ADDR_CONFIG_READ 196 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 197 #define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 198 #define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 199 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 200 #define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 201 #define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a 202 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 203 #define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 204 #define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 205 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L 206 #define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 207 #define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L 208 //VPEC_PROCESS_QUANTUM0 209 #define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 210 #define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 211 #define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 212 #define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 213 #define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL 214 #define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L 215 #define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L 216 #define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L 217 //VPEC_PROCESS_QUANTUM1 218 #define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 219 #define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 220 #define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 221 #define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 222 #define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL 223 #define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L 224 #define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L 225 #define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L 226 //VPEC_CONTEXT_SWITCH_THRESHOLD 227 #define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD__SHIFT 0x0 228 #define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD__SHIFT 0x2 229 #define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD__SHIFT 0x4 230 #define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD__SHIFT 0x6 231 #define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK 0x00000003L 232 #define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK 0x0000000CL 233 #define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK 0x00000030L 234 #define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK 0x000000C0L 235 //VPEC_GLOBAL_QUANTUM 236 #define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 237 #define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 238 #define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL 239 #define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L 240 //VPEC_WATCHDOG_CNTL 241 #define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 242 #define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 243 #define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL 244 #define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L 245 //VPEC_ATOMIC_CNTL 246 #define VPEC_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 247 #define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 248 #define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 249 #define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 250 //VPEC_UCODE_VERSION 251 #define VPEC_UCODE_VERSION__T0_UCODE_VERSION__SHIFT 0x0 252 #define VPEC_UCODE_VERSION__T1_UCODE_VERSION__SHIFT 0x10 253 #define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK 0x0000FFFFL 254 #define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK 0xFFFF0000L 255 //VPEC_MEMREQ_BURST_CNTL 256 #define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST__SHIFT 0x0 257 #define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST__SHIFT 0x2 258 #define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST__SHIFT 0x4 259 #define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST__SHIFT 0x6 260 #define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE__SHIFT 0x8 261 #define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK 0x00000003L 262 #define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK 0x0000000CL 263 #define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK 0x00000030L 264 #define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK 0x000000C0L 265 #define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK 0x00000700L 266 //VPEC_TIMESTAMP_CNTL 267 #define VPEC_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 268 #define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L 269 //VPEC_GLOBAL_TIMESTAMP_LO 270 #define VPEC_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 271 #define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL 272 //VPEC_GLOBAL_TIMESTAMP_HI 273 #define VPEC_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 274 #define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL 275 //VPEC_FREEZE 276 #define VPEC_FREEZE__PREEMPT__SHIFT 0x0 277 #define VPEC_FREEZE__FREEZE__SHIFT 0x4 278 #define VPEC_FREEZE__FROZEN__SHIFT 0x5 279 #define VPEC_FREEZE__F32_FREEZE__SHIFT 0x6 280 #define VPEC_FREEZE__PREEMPT_MASK 0x00000001L 281 #define VPEC_FREEZE__FREEZE_MASK 0x00000010L 282 #define VPEC_FREEZE__FROZEN_MASK 0x00000020L 283 #define VPEC_FREEZE__F32_FREEZE_MASK 0x00000040L 284 //VPEC_CE_CTRL 285 #define VPEC_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 286 #define VPEC_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 287 #define VPEC_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 288 #define VPEC_CE_CTRL__RESERVED__SHIFT 0x8 289 #define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 290 #define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 291 #define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 292 #define VPEC_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 293 //VPEC_RELAX_ORDERING_LUT 294 #define VPEC_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 295 #define VPEC_RELAX_ORDERING_LUT__VPE__SHIFT 0x1 296 #define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2__SHIFT 0x2 297 #define VPEC_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 298 #define VPEC_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 299 #define VPEC_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 300 #define VPEC_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 301 #define VPEC_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 302 #define VPEC_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 303 #define VPEC_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 304 #define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11__SHIFT 0xb 305 #define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12__SHIFT 0xc 306 #define VPEC_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 307 #define VPEC_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 308 #define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 309 #define VPEC_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 310 #define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29__SHIFT 0x1d 311 #define VPEC_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 312 #define VPEC_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 313 #define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 314 #define VPEC_RELAX_ORDERING_LUT__VPE_MASK 0x00000002L 315 #define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK 0x00000004L 316 #define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 317 #define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 318 #define VPEC_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 319 #define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 320 #define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 321 #define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 322 #define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 323 #define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK 0x00000800L 324 #define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK 0x00001000L 325 #define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 326 #define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 327 #define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 328 #define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 329 #define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK 0x20000000L 330 #define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 331 #define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 332 //VPEC_CREDIT_CNTL 333 #define VPEC_CREDIT_CNTL__DRM_CREDIT__SHIFT 0x0 334 #define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 335 #define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 336 #define VPEC_CREDIT_CNTL__DRM_CREDIT_MASK 0x0000007FL 337 #define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 338 #define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 339 //VPEC_SCRATCH_RAM_DATA 340 #define VPEC_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 341 #define VPEC_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 342 //VPEC_SCRATCH_RAM_ADDR 343 #define VPEC_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 344 #define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 345 //VPEC_QUEUE_RESET_REQ 346 #define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 347 #define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 348 #define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 349 #define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 350 #define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 351 #define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 352 #define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 353 #define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 354 #define VPEC_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 355 #define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L 356 #define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L 357 #define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L 358 #define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L 359 #define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L 360 #define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L 361 #define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L 362 #define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L 363 #define VPEC_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L 364 //VPEC_PERFCNT_PERFCOUNTER0_CFG 365 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 366 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 367 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 368 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 369 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 370 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 371 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 372 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 373 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 374 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 375 //VPEC_PERFCNT_PERFCOUNTER1_CFG 376 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 377 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 378 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 379 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 380 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 381 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 382 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 383 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 384 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 385 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 386 //VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL 387 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 388 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 389 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 390 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 391 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 392 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 393 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 394 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 395 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 396 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 397 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 398 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 399 //VPEC_PERFCNT_MISC_CNTL 400 #define VPEC_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 401 #define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10 402 #define VPEC_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 403 #define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L 404 //VPEC_PERFCNT_PERFCOUNTER_LO 405 #define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 406 #define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 407 //VPEC_PERFCNT_PERFCOUNTER_HI 408 #define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 409 #define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 410 #define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 411 #define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 412 //VPEC_DEBUG_INDEX 413 #define VPEC_DEBUG_INDEX__INDEX__SHIFT 0x0 414 #define VPEC_DEBUG_INDEX__INDEX_MASK 0xFFFFFFFFL 415 //VPEC_DEBUG_DATA 416 #define VPEC_DEBUG_DATA__DATA__SHIFT 0x0 417 #define VPEC_DEBUG_DATA__DATA_MASK 0xFFFFFFFFL 418 //VPEC_CRC_CTRL 419 #define VPEC_CRC_CTRL__INDEX__SHIFT 0x0 420 #define VPEC_CRC_CTRL__START__SHIFT 0x1f 421 #define VPEC_CRC_CTRL__INDEX_MASK 0x0000FFFFL 422 #define VPEC_CRC_CTRL__START_MASK 0x80000000L 423 //VPEC_CRC_DATA 424 #define VPEC_CRC_DATA__DATA__SHIFT 0x0 425 #define VPEC_CRC_DATA__DATA_MASK 0xFFFFFFFFL 426 //VPEC_PUB_DUMMY0 427 #define VPEC_PUB_DUMMY0__VALUE__SHIFT 0x0 428 #define VPEC_PUB_DUMMY0__VALUE_MASK 0xFFFFFFFFL 429 //VPEC_PUB_DUMMY1 430 #define VPEC_PUB_DUMMY1__VALUE__SHIFT 0x0 431 #define VPEC_PUB_DUMMY1__VALUE_MASK 0xFFFFFFFFL 432 //VPEC_PUB_DUMMY2 433 #define VPEC_PUB_DUMMY2__VALUE__SHIFT 0x0 434 #define VPEC_PUB_DUMMY2__VALUE_MASK 0xFFFFFFFFL 435 //VPEC_PUB_DUMMY3 436 #define VPEC_PUB_DUMMY3__VALUE__SHIFT 0x0 437 #define VPEC_PUB_DUMMY3__VALUE_MASK 0xFFFFFFFFL 438 //VPEC_PUB_DUMMY4 439 #define VPEC_PUB_DUMMY4__VALUE__SHIFT 0x0 440 #define VPEC_PUB_DUMMY4__VALUE_MASK 0xFFFFFFFFL 441 //VPEC_PUB_DUMMY5 442 #define VPEC_PUB_DUMMY5__VALUE__SHIFT 0x0 443 #define VPEC_PUB_DUMMY5__VALUE_MASK 0xFFFFFFFFL 444 //VPEC_PUB_DUMMY6 445 #define VPEC_PUB_DUMMY6__VALUE__SHIFT 0x0 446 #define VPEC_PUB_DUMMY6__VALUE_MASK 0xFFFFFFFFL 447 //VPEC_PUB_DUMMY7 448 #define VPEC_PUB_DUMMY7__VALUE__SHIFT 0x0 449 #define VPEC_PUB_DUMMY7__VALUE_MASK 0xFFFFFFFFL 450 //VPEC_UCODE1_CHECKSUM 451 #define VPEC_UCODE1_CHECKSUM__DATA__SHIFT 0x0 452 #define VPEC_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL 453 //VPEC_VERSION 454 #define VPEC_VERSION__MINVER__SHIFT 0x0 455 #define VPEC_VERSION__MAJVER__SHIFT 0x8 456 #define VPEC_VERSION__REV__SHIFT 0x10 457 #define VPEC_VERSION__MINVER_MASK 0x0000007FL 458 #define VPEC_VERSION__MAJVER_MASK 0x00007F00L 459 #define VPEC_VERSION__REV_MASK 0x003F0000L 460 //VPEC_UCODE_CHECKSUM 461 #define VPEC_UCODE_CHECKSUM__DATA__SHIFT 0x0 462 #define VPEC_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 463 //VPEC_CLOCK_GATING_STATUS 464 #define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 465 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS__SHIFT 0x2 466 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS__SHIFT 0x3 467 #define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS__SHIFT 0x4 468 #define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x5 469 #define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x6 470 #define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L 471 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK 0x00000004L 472 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK 0x00000008L 473 #define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK 0x00000010L 474 #define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000020L 475 #define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000040L 476 //VPEC_RB_RPTR_FETCH 477 #define VPEC_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 478 #define VPEC_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 479 //VPEC_RB_RPTR_FETCH_HI 480 #define VPEC_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 481 #define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 482 //VPEC_IB_OFFSET_FETCH 483 #define VPEC_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 484 #define VPEC_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 485 //VPEC_CMDIB_OFFSET_FETCH 486 #define VPEC_CMDIB_OFFSET_FETCH__OFFSET__SHIFT 0x2 487 #define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 488 //VPEC_ATOMIC_PREOP_LO 489 #define VPEC_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 490 #define VPEC_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 491 //VPEC_ATOMIC_PREOP_HI 492 #define VPEC_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 493 #define VPEC_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 494 //VPEC_CE_BUSY 495 #define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY__SHIFT 0x0 496 #define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY__SHIFT 0x1 497 #define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY__SHIFT 0x10 498 #define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK 0x00000001L 499 #define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK 0x00000002L 500 #define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK 0x00010000L 501 //VPEC_F32_COUNTER 502 #define VPEC_F32_COUNTER__VALUE__SHIFT 0x0 503 #define VPEC_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 504 //VPEC_HOLE_ADDR_LO 505 #define VPEC_HOLE_ADDR_LO__VALUE__SHIFT 0x0 506 #define VPEC_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL 507 //VPEC_HOLE_ADDR_HI 508 #define VPEC_HOLE_ADDR_HI__VALUE__SHIFT 0x0 509 #define VPEC_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL 510 //VPEC_ERROR_LOG 511 #define VPEC_ERROR_LOG__OVERRIDE__SHIFT 0x0 512 #define VPEC_ERROR_LOG__STATUS__SHIFT 0x10 513 #define VPEC_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 514 #define VPEC_ERROR_LOG__STATUS_MASK 0xFFFF0000L 515 //VPEC_INT_STATUS 516 #define VPEC_INT_STATUS__DATA__SHIFT 0x0 517 #define VPEC_INT_STATUS__DATA_MASK 0xFFFFFFFFL 518 //VPEC_STATUS 519 #define VPEC_STATUS__IDLE__SHIFT 0x0 520 #define VPEC_STATUS__REG_IDLE__SHIFT 0x1 521 #define VPEC_STATUS__RB_EMPTY__SHIFT 0x2 522 #define VPEC_STATUS__RB_FULL__SHIFT 0x3 523 #define VPEC_STATUS__RB_CMD_IDLE__SHIFT 0x4 524 #define VPEC_STATUS__RB_CMD_FULL__SHIFT 0x5 525 #define VPEC_STATUS__IB_CMD_IDLE__SHIFT 0x6 526 #define VPEC_STATUS__IB_CMD_FULL__SHIFT 0x7 527 #define VPEC_STATUS__BLOCK_IDLE__SHIFT 0x8 528 #define VPEC_STATUS__INSIDE_VPEP_CONFIG__SHIFT 0x9 529 #define VPEC_STATUS__EX_IDLE__SHIFT 0xa 530 #define VPEC_STATUS__RESERVED_11_11__SHIFT 0xb 531 #define VPEC_STATUS__PACKET_READY__SHIFT 0xc 532 #define VPEC_STATUS__MC_WR_IDLE__SHIFT 0xd 533 #define VPEC_STATUS__SRBM_IDLE__SHIFT 0xe 534 #define VPEC_STATUS__CONTEXT_EMPTY__SHIFT 0xf 535 #define VPEC_STATUS__INSIDE_IB__SHIFT 0x10 536 #define VPEC_STATUS__RB_MC_RREQ_IDLE__SHIFT 0x11 537 #define VPEC_STATUS__IB_MC_RREQ_IDLE__SHIFT 0x12 538 #define VPEC_STATUS__MC_RD_IDLE__SHIFT 0x13 539 #define VPEC_STATUS__DELTA_RPTR_EMPTY__SHIFT 0x14 540 #define VPEC_STATUS__MC_RD_RET_STALL__SHIFT 0x15 541 #define VPEC_STATUS__RESERVED_22_22__SHIFT 0x16 542 #define VPEC_STATUS__RESERVED_23_23__SHIFT 0x17 543 #define VPEC_STATUS__RESERVED_24_24__SHIFT 0x18 544 #define VPEC_STATUS__PREV_CMD_IDLE__SHIFT 0x19 545 #define VPEC_STATUS__RESERVED_26_26__SHIFT 0x1a 546 #define VPEC_STATUS__RESERVED_27_27__SHIFT 0x1b 547 #define VPEC_STATUS__RESERVED_29_28__SHIFT 0x1c 548 #define VPEC_STATUS__INT_IDLE__SHIFT 0x1e 549 #define VPEC_STATUS__INT_REQ_STALL__SHIFT 0x1f 550 #define VPEC_STATUS__IDLE_MASK 0x00000001L 551 #define VPEC_STATUS__REG_IDLE_MASK 0x00000002L 552 #define VPEC_STATUS__RB_EMPTY_MASK 0x00000004L 553 #define VPEC_STATUS__RB_FULL_MASK 0x00000008L 554 #define VPEC_STATUS__RB_CMD_IDLE_MASK 0x00000010L 555 #define VPEC_STATUS__RB_CMD_FULL_MASK 0x00000020L 556 #define VPEC_STATUS__IB_CMD_IDLE_MASK 0x00000040L 557 #define VPEC_STATUS__IB_CMD_FULL_MASK 0x00000080L 558 #define VPEC_STATUS__BLOCK_IDLE_MASK 0x00000100L 559 #define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK 0x00000200L 560 #define VPEC_STATUS__EX_IDLE_MASK 0x00000400L 561 #define VPEC_STATUS__RESERVED_11_11_MASK 0x00000800L 562 #define VPEC_STATUS__PACKET_READY_MASK 0x00001000L 563 #define VPEC_STATUS__MC_WR_IDLE_MASK 0x00002000L 564 #define VPEC_STATUS__SRBM_IDLE_MASK 0x00004000L 565 #define VPEC_STATUS__CONTEXT_EMPTY_MASK 0x00008000L 566 #define VPEC_STATUS__INSIDE_IB_MASK 0x00010000L 567 #define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK 0x00020000L 568 #define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK 0x00040000L 569 #define VPEC_STATUS__MC_RD_IDLE_MASK 0x00080000L 570 #define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK 0x00100000L 571 #define VPEC_STATUS__MC_RD_RET_STALL_MASK 0x00200000L 572 #define VPEC_STATUS__RESERVED_22_22_MASK 0x00400000L 573 #define VPEC_STATUS__RESERVED_23_23_MASK 0x00800000L 574 #define VPEC_STATUS__RESERVED_24_24_MASK 0x01000000L 575 #define VPEC_STATUS__PREV_CMD_IDLE_MASK 0x02000000L 576 #define VPEC_STATUS__RESERVED_26_26_MASK 0x04000000L 577 #define VPEC_STATUS__RESERVED_27_27_MASK 0x08000000L 578 #define VPEC_STATUS__RESERVED_29_28_MASK 0x30000000L 579 #define VPEC_STATUS__INT_IDLE_MASK 0x40000000L 580 #define VPEC_STATUS__INT_REQ_STALL_MASK 0x80000000L 581 //VPEC_STATUS1 582 #define VPEC_STATUS1__CE_IP0_WREQ_IDLE__SHIFT 0x0 583 #define VPEC_STATUS1__CE_IP0_WR_IDLE__SHIFT 0x1 584 #define VPEC_STATUS1__CE_IP0_SPLIT_IDLE__SHIFT 0x2 585 #define VPEC_STATUS1__CE_IP0_RREQ_IDLE__SHIFT 0x3 586 #define VPEC_STATUS1__CE_IP0_OUT_IDLE__SHIFT 0x4 587 #define VPEC_STATUS1__CE_IP0_IN_IDLE__SHIFT 0x5 588 #define VPEC_STATUS1__CE_IP0_DST_IDLE__SHIFT 0x6 589 #define VPEC_STATUS1__CE_IP0_CMD_IDLE__SHIFT 0x7 590 #define VPEC_STATUS1__CE_IP1_WREQ_IDLE__SHIFT 0x8 591 #define VPEC_STATUS1__CE_IP1_WR_IDLE__SHIFT 0x9 592 #define VPEC_STATUS1__CE_IP1_SPLIT_IDLE__SHIFT 0xa 593 #define VPEC_STATUS1__CE_IP1_RREQ_IDLE__SHIFT 0xb 594 #define VPEC_STATUS1__CE_IP1_OUT_IDLE__SHIFT 0xc 595 #define VPEC_STATUS1__CE_IP1_IN_IDLE__SHIFT 0xd 596 #define VPEC_STATUS1__CE_IP1_DST_IDLE__SHIFT 0xe 597 #define VPEC_STATUS1__CE_IP1_CMD_IDLE__SHIFT 0xf 598 #define VPEC_STATUS1__CE_OP0_WR_IDLE__SHIFT 0x10 599 #define VPEC_STATUS1__CE_OP0_CMD_IDLE__SHIFT 0x11 600 #define VPEC_STATUS1__CE_IP0_AFIFO_FULL__SHIFT 0x12 601 #define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL__SHIFT 0x13 602 #define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL__SHIFT 0x14 603 #define VPEC_STATUS1__CE_IP1_AFIFO_FULL__SHIFT 0x15 604 #define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL__SHIFT 0x16 605 #define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL__SHIFT 0x17 606 #define VPEC_STATUS1__EX_START__SHIFT 0x18 607 #define VPEC_STATUS1__CE_RD_STALL__SHIFT 0x19 608 #define VPEC_STATUS1__CE_IP0_WR_STALL__SHIFT 0x1a 609 #define VPEC_STATUS1__CE_IP1_WR_STALL__SHIFT 0x1b 610 #define VPEC_STATUS1__RESERVED_28_28__SHIFT 0x1c 611 #define VPEC_STATUS1__VPEC_IDLE__SHIFT 0x1d 612 #define VPEC_STATUS1__PG_STATUS__SHIFT 0x1e 613 #define VPEC_STATUS1__CE_IP0_WREQ_IDLE_MASK 0x00000001L 614 #define VPEC_STATUS1__CE_IP0_WR_IDLE_MASK 0x00000002L 615 #define VPEC_STATUS1__CE_IP0_SPLIT_IDLE_MASK 0x00000004L 616 #define VPEC_STATUS1__CE_IP0_RREQ_IDLE_MASK 0x00000008L 617 #define VPEC_STATUS1__CE_IP0_OUT_IDLE_MASK 0x00000010L 618 #define VPEC_STATUS1__CE_IP0_IN_IDLE_MASK 0x00000020L 619 #define VPEC_STATUS1__CE_IP0_DST_IDLE_MASK 0x00000040L 620 #define VPEC_STATUS1__CE_IP0_CMD_IDLE_MASK 0x00000080L 621 #define VPEC_STATUS1__CE_IP1_WREQ_IDLE_MASK 0x00000100L 622 #define VPEC_STATUS1__CE_IP1_WR_IDLE_MASK 0x00000200L 623 #define VPEC_STATUS1__CE_IP1_SPLIT_IDLE_MASK 0x00000400L 624 #define VPEC_STATUS1__CE_IP1_RREQ_IDLE_MASK 0x00000800L 625 #define VPEC_STATUS1__CE_IP1_OUT_IDLE_MASK 0x00001000L 626 #define VPEC_STATUS1__CE_IP1_IN_IDLE_MASK 0x00002000L 627 #define VPEC_STATUS1__CE_IP1_DST_IDLE_MASK 0x00004000L 628 #define VPEC_STATUS1__CE_IP1_CMD_IDLE_MASK 0x00008000L 629 #define VPEC_STATUS1__CE_OP0_WR_IDLE_MASK 0x00010000L 630 #define VPEC_STATUS1__CE_OP0_CMD_IDLE_MASK 0x00020000L 631 #define VPEC_STATUS1__CE_IP0_AFIFO_FULL_MASK 0x00040000L 632 #define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL_MASK 0x00080000L 633 #define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL_MASK 0x00100000L 634 #define VPEC_STATUS1__CE_IP1_AFIFO_FULL_MASK 0x00200000L 635 #define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL_MASK 0x00400000L 636 #define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL_MASK 0x00800000L 637 #define VPEC_STATUS1__EX_START_MASK 0x01000000L 638 #define VPEC_STATUS1__CE_RD_STALL_MASK 0x02000000L 639 #define VPEC_STATUS1__CE_IP0_WR_STALL_MASK 0x04000000L 640 #define VPEC_STATUS1__CE_IP1_WR_STALL_MASK 0x08000000L 641 #define VPEC_STATUS1__RESERVED_28_28_MASK 0x10000000L 642 #define VPEC_STATUS1__VPEC_IDLE_MASK 0x20000000L 643 #define VPEC_STATUS1__PG_STATUS_MASK 0xC0000000L 644 //VPEC_STATUS2 645 #define VPEC_STATUS2__ID__SHIFT 0x0 646 #define VPEC_STATUS2__TH0F32_INSTR_PTR__SHIFT 0x2 647 #define VPEC_STATUS2__CMD_OP__SHIFT 0x10 648 #define VPEC_STATUS2__ID_MASK 0x00000003L 649 #define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK 0x0000FFFCL 650 #define VPEC_STATUS2__CMD_OP_MASK 0xFFFF0000L 651 //VPEC_STATUS3 652 #define VPEC_STATUS3__CMD_OP_STATUS__SHIFT 0x0 653 #define VPEC_STATUS3__RESERVED_19_16__SHIFT 0x10 654 #define VPEC_STATUS3__EXCEPTION_IDLE__SHIFT 0x14 655 #define VPEC_STATUS3__RESERVED_21_21__SHIFT 0x15 656 #define VPEC_STATUS3__RESERVED_22_22__SHIFT 0x16 657 #define VPEC_STATUS3__RESERVED_23_23__SHIFT 0x17 658 #define VPEC_STATUS3__RESERVED_24_24__SHIFT 0x18 659 #define VPEC_STATUS3__RESERVED_25_25__SHIFT 0x19 660 #define VPEC_STATUS3__INT_QUEUE_ID__SHIFT 0x1a 661 #define VPEC_STATUS3__RESERVED_31_30__SHIFT 0x1e 662 #define VPEC_STATUS3__CMD_OP_STATUS_MASK 0x0000FFFFL 663 #define VPEC_STATUS3__RESERVED_19_16_MASK 0x000F0000L 664 #define VPEC_STATUS3__EXCEPTION_IDLE_MASK 0x00100000L 665 #define VPEC_STATUS3__RESERVED_21_21_MASK 0x00200000L 666 #define VPEC_STATUS3__RESERVED_22_22_MASK 0x00400000L 667 #define VPEC_STATUS3__RESERVED_23_23_MASK 0x00800000L 668 #define VPEC_STATUS3__RESERVED_24_24_MASK 0x01000000L 669 #define VPEC_STATUS3__RESERVED_25_25_MASK 0x02000000L 670 #define VPEC_STATUS3__INT_QUEUE_ID_MASK 0x3C000000L 671 #define VPEC_STATUS3__RESERVED_31_30_MASK 0xC0000000L 672 //VPEC_STATUS4 673 #define VPEC_STATUS4__IDLE__SHIFT 0x0 674 #define VPEC_STATUS4__IH_OUTSTANDING__SHIFT 0x2 675 #define VPEC_STATUS4__RESERVED_3_3__SHIFT 0x3 676 #define VPEC_STATUS4__CH_RD_OUTSTANDING__SHIFT 0x4 677 #define VPEC_STATUS4__CH_WR_OUTSTANDING__SHIFT 0x5 678 #define VPEC_STATUS4__RESERVED_6_6__SHIFT 0x6 679 #define VPEC_STATUS4__RESERVED_7_7__SHIFT 0x7 680 #define VPEC_STATUS4__RESERVED_8_8__SHIFT 0x8 681 #define VPEC_STATUS4__RESERVED_9_9__SHIFT 0x9 682 #define VPEC_STATUS4__REG_POLLING__SHIFT 0xa 683 #define VPEC_STATUS4__MEM_POLLING__SHIFT 0xb 684 #define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING__SHIFT 0xc 685 #define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING__SHIFT 0xd 686 #define VPEC_STATUS4__RESERVED_15_14__SHIFT 0xe 687 #define VPEC_STATUS4__ACTIVE_QUEUE_ID__SHIFT 0x10 688 #define VPEC_STATUS4__RESERVED_27_20__SHIFT 0x14 689 #define VPEC_STATUS4__IDLE_MASK 0x00000001L 690 #define VPEC_STATUS4__IH_OUTSTANDING_MASK 0x00000004L 691 #define VPEC_STATUS4__RESERVED_3_3_MASK 0x00000008L 692 #define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK 0x00000010L 693 #define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK 0x00000020L 694 #define VPEC_STATUS4__RESERVED_6_6_MASK 0x00000040L 695 #define VPEC_STATUS4__RESERVED_7_7_MASK 0x00000080L 696 #define VPEC_STATUS4__RESERVED_8_8_MASK 0x00000100L 697 #define VPEC_STATUS4__RESERVED_9_9_MASK 0x00000200L 698 #define VPEC_STATUS4__REG_POLLING_MASK 0x00000400L 699 #define VPEC_STATUS4__MEM_POLLING_MASK 0x00000800L 700 #define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK 0x00001000L 701 #define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK 0x00002000L 702 #define VPEC_STATUS4__RESERVED_15_14_MASK 0x0000C000L 703 #define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK 0x000F0000L 704 #define VPEC_STATUS4__RESERVED_27_20_MASK 0x0FF00000L 705 //VPEC_STATUS5 706 #define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 707 #define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 708 #define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 709 #define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 710 #define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 711 #define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 712 #define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 713 #define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 714 #define VPEC_STATUS5__RESERVED_27_16__SHIFT 0x10 715 #define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L 716 #define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L 717 #define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L 718 #define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L 719 #define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L 720 #define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L 721 #define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L 722 #define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L 723 #define VPEC_STATUS5__RESERVED_27_16_MASK 0x000F0000L 724 //VPEC_STATUS6 725 #define VPEC_STATUS6__ID__SHIFT 0x0 726 #define VPEC_STATUS6__TH1F32_INSTR_PTR__SHIFT 0x2 727 #define VPEC_STATUS6__TH1_EXCEPTION__SHIFT 0x10 728 #define VPEC_STATUS6__ID_MASK 0x00000003L 729 #define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK 0x0000FFFCL 730 #define VPEC_STATUS6__TH1_EXCEPTION_MASK 0xFFFF0000L 731 //VPEC_STATUS7 732 #define VPEC_STATUS7__TH0_DBG_STATUS__SHIFT 0x0 733 #define VPEC_STATUS7__TH0_DBG_STATUS_MASK 0xFFFFFFFFL 734 //VPEC_INST 735 #define VPEC_INST__ID__SHIFT 0x0 736 #define VPEC_INST__RESERVED__SHIFT 0x1 737 #define VPEC_INST__ID_MASK 0x00000001L 738 #define VPEC_INST__RESERVED_MASK 0xFFFFFFFEL 739 //VPEC_QUEUE_STATUS0 740 #define VPEC_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 741 #define VPEC_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 742 #define VPEC_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 743 #define VPEC_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc 744 #define VPEC_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 745 #define VPEC_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 746 #define VPEC_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 747 #define VPEC_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c 748 #define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL 749 #define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L 750 #define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L 751 #define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L 752 #define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L 753 #define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L 754 #define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L 755 #define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L 756 //VPEC_QUEUE_HANG_STATUS 757 #define VPEC_QUEUE_HANG_STATUS__F30T0_HANG__SHIFT 0x0 758 #define VPEC_QUEUE_HANG_STATUS__CE_HANG__SHIFT 0x1 759 #define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH__SHIFT 0x2 760 #define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE__SHIFT 0x3 761 #define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR__SHIFT 0x4 762 #define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK 0x00000001L 763 #define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK 0x00000002L 764 #define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK 0x00000004L 765 #define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE_MASK 0x00000008L 766 #define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK 0x00000010L 767 //VPEC_QUEUE0_RB_CNTL 768 #define VPEC_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 769 #define VPEC_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 770 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 771 #define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 772 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 773 #define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 774 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 775 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 776 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 777 #define VPEC_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 778 #define VPEC_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 779 #define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 780 #define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 781 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 782 #define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 783 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 784 #define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 785 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 786 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 787 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 788 #define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L 789 #define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L 790 //VPEC_QUEUE0_SCHEDULE_CNTL 791 #define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 792 #define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 793 #define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 794 #define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 795 #define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 796 #define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 797 #define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 798 #define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 799 //VPEC_QUEUE0_RB_BASE 800 #define VPEC_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 801 #define VPEC_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 802 //VPEC_QUEUE0_RB_BASE_HI 803 #define VPEC_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 804 #define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 805 //VPEC_QUEUE0_RB_RPTR 806 #define VPEC_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 807 #define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 808 //VPEC_QUEUE0_RB_RPTR_HI 809 #define VPEC_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 810 #define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 811 //VPEC_QUEUE0_RB_WPTR 812 #define VPEC_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 813 #define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 814 //VPEC_QUEUE0_RB_WPTR_HI 815 #define VPEC_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 816 #define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 817 //VPEC_QUEUE0_RB_RPTR_ADDR_HI 818 #define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 819 #define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 820 //VPEC_QUEUE0_RB_RPTR_ADDR_LO 821 #define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 822 #define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 823 //VPEC_QUEUE0_RB_AQL_CNTL 824 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 825 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 826 #define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 827 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 828 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 829 #define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 830 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 831 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 832 #define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 833 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 834 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 835 #define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 836 //VPEC_QUEUE0_MINOR_PTR_UPDATE 837 #define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 838 #define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 839 //VPEC_QUEUE0_CD_INFO 840 #define VPEC_QUEUE0_CD_INFO__CD_INFO__SHIFT 0x0 841 #define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 842 //VPEC_QUEUE0_RB_PREEMPT 843 #define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 844 #define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 845 //VPEC_QUEUE0_SKIP_CNTL 846 #define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 847 #define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 848 //VPEC_QUEUE0_DOORBELL 849 #define VPEC_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c 850 #define VPEC_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e 851 #define VPEC_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L 852 #define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L 853 //VPEC_QUEUE0_DOORBELL_OFFSET 854 #define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 855 #define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 856 //VPEC_QUEUE0_DUMMY0 857 #define VPEC_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0 858 #define VPEC_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 859 //VPEC_QUEUE0_DUMMY1 860 #define VPEC_QUEUE0_DUMMY1__VALUE__SHIFT 0x0 861 #define VPEC_QUEUE0_DUMMY1__VALUE_MASK 0xFFFFFFFFL 862 //VPEC_QUEUE0_DUMMY2 863 #define VPEC_QUEUE0_DUMMY2__VALUE__SHIFT 0x0 864 #define VPEC_QUEUE0_DUMMY2__VALUE_MASK 0xFFFFFFFFL 865 //VPEC_QUEUE0_DUMMY3 866 #define VPEC_QUEUE0_DUMMY3__VALUE__SHIFT 0x0 867 #define VPEC_QUEUE0_DUMMY3__VALUE_MASK 0xFFFFFFFFL 868 //VPEC_QUEUE0_DUMMY4 869 #define VPEC_QUEUE0_DUMMY4__VALUE__SHIFT 0x0 870 #define VPEC_QUEUE0_DUMMY4__VALUE_MASK 0xFFFFFFFFL 871 //VPEC_QUEUE0_IB_CNTL 872 #define VPEC_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 873 #define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 874 #define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 875 #define VPEC_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 876 #define VPEC_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f 877 #define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 878 #define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 879 #define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 880 #define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 881 #define VPEC_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L 882 //VPEC_QUEUE0_IB_RPTR 883 #define VPEC_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 884 #define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 885 //VPEC_QUEUE0_IB_OFFSET 886 #define VPEC_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 887 #define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 888 //VPEC_QUEUE0_IB_BASE_LO 889 #define VPEC_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 890 #define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 891 //VPEC_QUEUE0_IB_BASE_HI 892 #define VPEC_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 893 #define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 894 //VPEC_QUEUE0_IB_SIZE 895 #define VPEC_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 896 #define VPEC_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL 897 //VPEC_QUEUE0_CMDIB_CNTL 898 #define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 899 #define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 900 #define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 901 #define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 902 #define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 903 #define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 904 #define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 905 #define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 906 #define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 907 #define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 908 //VPEC_QUEUE0_CMDIB_RPTR 909 #define VPEC_QUEUE0_CMDIB_RPTR__OFFSET__SHIFT 0x2 910 #define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 911 //VPEC_QUEUE0_CMDIB_OFFSET 912 #define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET__SHIFT 0x2 913 #define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 914 //VPEC_QUEUE0_CMDIB_BASE_LO 915 #define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR__SHIFT 0x5 916 #define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 917 //VPEC_QUEUE0_CMDIB_BASE_HI 918 #define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR__SHIFT 0x0 919 #define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 920 //VPEC_QUEUE0_CMDIB_SIZE 921 #define VPEC_QUEUE0_CMDIB_SIZE__SIZE__SHIFT 0x0 922 #define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 923 //VPEC_QUEUE0_CSA_ADDR_LO 924 #define VPEC_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x0 925 #define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 926 //VPEC_QUEUE0_CSA_ADDR_HI 927 #define VPEC_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 928 #define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 929 //VPEC_QUEUE0_CONTEXT_STATUS 930 #define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 931 #define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 932 #define VPEC_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 933 #define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 934 #define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 935 #define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 936 #define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 937 #define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 938 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 939 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 940 #define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 941 #define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 942 #define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 943 #define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 944 #define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 945 #define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 946 #define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 947 #define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 948 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 949 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 950 //VPEC_QUEUE0_DOORBELL_LOG 951 #define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 952 #define VPEC_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 953 #define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 954 #define VPEC_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 955 //VPEC_QUEUE0_IB_SUB_REMAIN 956 #define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 957 #define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 958 //VPEC_QUEUE0_PREEMPT 959 #define VPEC_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 960 #define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 961 //VPEC_QUEUE1_RB_CNTL 962 #define VPEC_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 963 #define VPEC_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 964 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 965 #define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 966 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 967 #define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 968 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 969 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 970 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 971 #define VPEC_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 972 #define VPEC_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 973 #define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 974 #define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 975 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 976 #define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 977 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 978 #define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 979 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 980 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 981 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 982 #define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L 983 #define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L 984 //VPEC_QUEUE1_SCHEDULE_CNTL 985 #define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 986 #define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 987 #define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 988 #define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 989 #define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 990 #define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 991 #define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 992 #define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 993 //VPEC_QUEUE1_RB_BASE 994 #define VPEC_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 995 #define VPEC_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 996 //VPEC_QUEUE1_RB_BASE_HI 997 #define VPEC_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 998 #define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 999 //VPEC_QUEUE1_RB_RPTR 1000 #define VPEC_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 1001 #define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1002 //VPEC_QUEUE1_RB_RPTR_HI 1003 #define VPEC_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1004 #define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1005 //VPEC_QUEUE1_RB_WPTR 1006 #define VPEC_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 1007 #define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1008 //VPEC_QUEUE1_RB_WPTR_HI 1009 #define VPEC_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1010 #define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1011 //VPEC_QUEUE1_RB_RPTR_ADDR_HI 1012 #define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1013 #define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1014 //VPEC_QUEUE1_RB_RPTR_ADDR_LO 1015 #define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1016 #define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1017 //VPEC_QUEUE1_RB_AQL_CNTL 1018 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1019 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1020 #define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1021 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1022 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1023 #define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1024 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1025 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1026 #define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1027 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1028 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1029 #define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1030 //VPEC_QUEUE1_MINOR_PTR_UPDATE 1031 #define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1032 #define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1033 //VPEC_QUEUE1_CD_INFO 1034 #define VPEC_QUEUE1_CD_INFO__CD_INFO__SHIFT 0x0 1035 #define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1036 //VPEC_QUEUE1_RB_PREEMPT 1037 #define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1038 #define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1039 //VPEC_QUEUE1_SKIP_CNTL 1040 #define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1041 #define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1042 //VPEC_QUEUE1_DOORBELL 1043 #define VPEC_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c 1044 #define VPEC_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e 1045 #define VPEC_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L 1046 #define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L 1047 //VPEC_QUEUE1_DOORBELL_OFFSET 1048 #define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1049 #define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1050 //VPEC_QUEUE1_DUMMY0 1051 #define VPEC_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0 1052 #define VPEC_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1053 //VPEC_QUEUE1_DUMMY1 1054 #define VPEC_QUEUE1_DUMMY1__VALUE__SHIFT 0x0 1055 #define VPEC_QUEUE1_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1056 //VPEC_QUEUE1_DUMMY2 1057 #define VPEC_QUEUE1_DUMMY2__VALUE__SHIFT 0x0 1058 #define VPEC_QUEUE1_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1059 //VPEC_QUEUE1_DUMMY3 1060 #define VPEC_QUEUE1_DUMMY3__VALUE__SHIFT 0x0 1061 #define VPEC_QUEUE1_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1062 //VPEC_QUEUE1_DUMMY4 1063 #define VPEC_QUEUE1_DUMMY4__VALUE__SHIFT 0x0 1064 #define VPEC_QUEUE1_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1065 //VPEC_QUEUE1_IB_CNTL 1066 #define VPEC_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1067 #define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1068 #define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1069 #define VPEC_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 1070 #define VPEC_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f 1071 #define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1072 #define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1073 #define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1074 #define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1075 #define VPEC_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L 1076 //VPEC_QUEUE1_IB_RPTR 1077 #define VPEC_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 1078 #define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1079 //VPEC_QUEUE1_IB_OFFSET 1080 #define VPEC_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 1081 #define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1082 //VPEC_QUEUE1_IB_BASE_LO 1083 #define VPEC_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 1084 #define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1085 //VPEC_QUEUE1_IB_BASE_HI 1086 #define VPEC_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 1087 #define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1088 //VPEC_QUEUE1_IB_SIZE 1089 #define VPEC_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 1090 #define VPEC_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1091 //VPEC_QUEUE1_CMDIB_CNTL 1092 #define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1093 #define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1094 #define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1095 #define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1096 #define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 1097 #define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1098 #define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1099 #define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1100 #define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1101 #define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 1102 //VPEC_QUEUE1_CMDIB_RPTR 1103 #define VPEC_QUEUE1_CMDIB_RPTR__OFFSET__SHIFT 0x2 1104 #define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1105 //VPEC_QUEUE1_CMDIB_OFFSET 1106 #define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1107 #define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1108 //VPEC_QUEUE1_CMDIB_BASE_LO 1109 #define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1110 #define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1111 //VPEC_QUEUE1_CMDIB_BASE_HI 1112 #define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1113 #define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1114 //VPEC_QUEUE1_CMDIB_SIZE 1115 #define VPEC_QUEUE1_CMDIB_SIZE__SIZE__SHIFT 0x0 1116 #define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1117 //VPEC_QUEUE1_CSA_ADDR_LO 1118 #define VPEC_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x0 1119 #define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1120 //VPEC_QUEUE1_CSA_ADDR_HI 1121 #define VPEC_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1122 #define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1123 //VPEC_QUEUE1_CONTEXT_STATUS 1124 #define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1125 #define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1126 #define VPEC_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1127 #define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1128 #define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1129 #define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1130 #define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1131 #define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1132 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1133 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1134 #define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1135 #define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1136 #define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1137 #define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1138 #define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1139 #define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1140 #define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1141 #define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1142 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1143 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1144 //VPEC_QUEUE1_DOORBELL_LOG 1145 #define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1146 #define VPEC_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 1147 #define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1148 #define VPEC_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1149 //VPEC_QUEUE1_IB_SUB_REMAIN 1150 #define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1151 #define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1152 //VPEC_QUEUE1_PREEMPT 1153 #define VPEC_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1154 #define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1155 //VPEC_QUEUE2_RB_CNTL 1156 #define VPEC_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1157 #define VPEC_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 1158 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1159 #define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1160 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1161 #define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1162 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1163 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1164 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1165 #define VPEC_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 1166 #define VPEC_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 1167 #define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1168 #define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1169 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1170 #define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1171 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1172 #define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1173 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1174 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1175 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1176 #define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1177 #define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1178 //VPEC_QUEUE2_SCHEDULE_CNTL 1179 #define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1180 #define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1181 #define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1182 #define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1183 #define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1184 #define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1185 #define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1186 #define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1187 //VPEC_QUEUE2_RB_BASE 1188 #define VPEC_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 1189 #define VPEC_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1190 //VPEC_QUEUE2_RB_BASE_HI 1191 #define VPEC_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 1192 #define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1193 //VPEC_QUEUE2_RB_RPTR 1194 #define VPEC_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 1195 #define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1196 //VPEC_QUEUE2_RB_RPTR_HI 1197 #define VPEC_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1198 #define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1199 //VPEC_QUEUE2_RB_WPTR 1200 #define VPEC_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 1201 #define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1202 //VPEC_QUEUE2_RB_WPTR_HI 1203 #define VPEC_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1204 #define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1205 //VPEC_QUEUE2_RB_RPTR_ADDR_HI 1206 #define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1207 #define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1208 //VPEC_QUEUE2_RB_RPTR_ADDR_LO 1209 #define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1210 #define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1211 //VPEC_QUEUE2_RB_AQL_CNTL 1212 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1213 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1214 #define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1215 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1216 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1217 #define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1218 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1219 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1220 #define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1221 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1222 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1223 #define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1224 //VPEC_QUEUE2_MINOR_PTR_UPDATE 1225 #define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1226 #define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1227 //VPEC_QUEUE2_CD_INFO 1228 #define VPEC_QUEUE2_CD_INFO__CD_INFO__SHIFT 0x0 1229 #define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1230 //VPEC_QUEUE2_RB_PREEMPT 1231 #define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1232 #define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1233 //VPEC_QUEUE2_SKIP_CNTL 1234 #define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1235 #define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1236 //VPEC_QUEUE2_DOORBELL 1237 #define VPEC_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c 1238 #define VPEC_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e 1239 #define VPEC_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L 1240 #define VPEC_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L 1241 //VPEC_QUEUE2_DOORBELL_OFFSET 1242 #define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1243 #define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1244 //VPEC_QUEUE2_DUMMY0 1245 #define VPEC_QUEUE2_DUMMY0__DUMMY__SHIFT 0x0 1246 #define VPEC_QUEUE2_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1247 //VPEC_QUEUE2_DUMMY1 1248 #define VPEC_QUEUE2_DUMMY1__VALUE__SHIFT 0x0 1249 #define VPEC_QUEUE2_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1250 //VPEC_QUEUE2_DUMMY2 1251 #define VPEC_QUEUE2_DUMMY2__VALUE__SHIFT 0x0 1252 #define VPEC_QUEUE2_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1253 //VPEC_QUEUE2_DUMMY3 1254 #define VPEC_QUEUE2_DUMMY3__VALUE__SHIFT 0x0 1255 #define VPEC_QUEUE2_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1256 //VPEC_QUEUE2_DUMMY4 1257 #define VPEC_QUEUE2_DUMMY4__VALUE__SHIFT 0x0 1258 #define VPEC_QUEUE2_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1259 //VPEC_QUEUE2_IB_CNTL 1260 #define VPEC_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1261 #define VPEC_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1262 #define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1263 #define VPEC_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 1264 #define VPEC_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f 1265 #define VPEC_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1266 #define VPEC_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1267 #define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1268 #define VPEC_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1269 #define VPEC_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L 1270 //VPEC_QUEUE2_IB_RPTR 1271 #define VPEC_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 1272 #define VPEC_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1273 //VPEC_QUEUE2_IB_OFFSET 1274 #define VPEC_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 1275 #define VPEC_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1276 //VPEC_QUEUE2_IB_BASE_LO 1277 #define VPEC_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 1278 #define VPEC_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1279 //VPEC_QUEUE2_IB_BASE_HI 1280 #define VPEC_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 1281 #define VPEC_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1282 //VPEC_QUEUE2_IB_SIZE 1283 #define VPEC_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 1284 #define VPEC_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1285 //VPEC_QUEUE2_CMDIB_CNTL 1286 #define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1287 #define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1288 #define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1289 #define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1290 #define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 1291 #define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1292 #define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1293 #define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1294 #define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1295 #define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 1296 //VPEC_QUEUE2_CMDIB_RPTR 1297 #define VPEC_QUEUE2_CMDIB_RPTR__OFFSET__SHIFT 0x2 1298 #define VPEC_QUEUE2_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1299 //VPEC_QUEUE2_CMDIB_OFFSET 1300 #define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1301 #define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1302 //VPEC_QUEUE2_CMDIB_BASE_LO 1303 #define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1304 #define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1305 //VPEC_QUEUE2_CMDIB_BASE_HI 1306 #define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1307 #define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1308 //VPEC_QUEUE2_CMDIB_SIZE 1309 #define VPEC_QUEUE2_CMDIB_SIZE__SIZE__SHIFT 0x0 1310 #define VPEC_QUEUE2_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1311 //VPEC_QUEUE2_CSA_ADDR_LO 1312 #define VPEC_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x0 1313 #define VPEC_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1314 //VPEC_QUEUE2_CSA_ADDR_HI 1315 #define VPEC_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1316 #define VPEC_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1317 //VPEC_QUEUE2_CONTEXT_STATUS 1318 #define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1319 #define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1320 #define VPEC_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1321 #define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1322 #define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1323 #define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1324 #define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1325 #define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1326 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1327 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1328 #define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1329 #define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1330 #define VPEC_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1331 #define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1332 #define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1333 #define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1334 #define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1335 #define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1336 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1337 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1338 //VPEC_QUEUE2_DOORBELL_LOG 1339 #define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1340 #define VPEC_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 1341 #define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1342 #define VPEC_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1343 //VPEC_QUEUE2_IB_SUB_REMAIN 1344 #define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1345 #define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1346 //VPEC_QUEUE2_PREEMPT 1347 #define VPEC_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1348 #define VPEC_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1349 //VPEC_QUEUE3_RB_CNTL 1350 #define VPEC_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 1351 #define VPEC_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 1352 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1353 #define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1354 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1355 #define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1356 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1357 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1358 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1359 #define VPEC_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 1360 #define VPEC_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 1361 #define VPEC_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1362 #define VPEC_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1363 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1364 #define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1365 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1366 #define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1367 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1368 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1369 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1370 #define VPEC_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L 1371 #define VPEC_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L 1372 //VPEC_QUEUE3_SCHEDULE_CNTL 1373 #define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1374 #define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1375 #define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1376 #define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1377 #define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1378 #define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1379 #define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1380 #define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1381 //VPEC_QUEUE3_RB_BASE 1382 #define VPEC_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 1383 #define VPEC_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1384 //VPEC_QUEUE3_RB_BASE_HI 1385 #define VPEC_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 1386 #define VPEC_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1387 //VPEC_QUEUE3_RB_RPTR 1388 #define VPEC_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 1389 #define VPEC_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1390 //VPEC_QUEUE3_RB_RPTR_HI 1391 #define VPEC_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 1392 #define VPEC_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1393 //VPEC_QUEUE3_RB_WPTR 1394 #define VPEC_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 1395 #define VPEC_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1396 //VPEC_QUEUE3_RB_WPTR_HI 1397 #define VPEC_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 1398 #define VPEC_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1399 //VPEC_QUEUE3_RB_RPTR_ADDR_HI 1400 #define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1401 #define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1402 //VPEC_QUEUE3_RB_RPTR_ADDR_LO 1403 #define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1404 #define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1405 //VPEC_QUEUE3_RB_AQL_CNTL 1406 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1407 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1408 #define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1409 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1410 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1411 #define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1412 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1413 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1414 #define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1415 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1416 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1417 #define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1418 //VPEC_QUEUE3_MINOR_PTR_UPDATE 1419 #define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1420 #define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1421 //VPEC_QUEUE3_CD_INFO 1422 #define VPEC_QUEUE3_CD_INFO__CD_INFO__SHIFT 0x0 1423 #define VPEC_QUEUE3_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1424 //VPEC_QUEUE3_RB_PREEMPT 1425 #define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1426 #define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1427 //VPEC_QUEUE3_SKIP_CNTL 1428 #define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1429 #define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1430 //VPEC_QUEUE3_DOORBELL 1431 #define VPEC_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c 1432 #define VPEC_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e 1433 #define VPEC_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L 1434 #define VPEC_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L 1435 //VPEC_QUEUE3_DOORBELL_OFFSET 1436 #define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1437 #define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1438 //VPEC_QUEUE3_DUMMY0 1439 #define VPEC_QUEUE3_DUMMY0__DUMMY__SHIFT 0x0 1440 #define VPEC_QUEUE3_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1441 //VPEC_QUEUE3_DUMMY1 1442 #define VPEC_QUEUE3_DUMMY1__VALUE__SHIFT 0x0 1443 #define VPEC_QUEUE3_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1444 //VPEC_QUEUE3_DUMMY2 1445 #define VPEC_QUEUE3_DUMMY2__VALUE__SHIFT 0x0 1446 #define VPEC_QUEUE3_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1447 //VPEC_QUEUE3_DUMMY3 1448 #define VPEC_QUEUE3_DUMMY3__VALUE__SHIFT 0x0 1449 #define VPEC_QUEUE3_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1450 //VPEC_QUEUE3_DUMMY4 1451 #define VPEC_QUEUE3_DUMMY4__VALUE__SHIFT 0x0 1452 #define VPEC_QUEUE3_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1453 //VPEC_QUEUE3_IB_CNTL 1454 #define VPEC_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 1455 #define VPEC_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1456 #define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1457 #define VPEC_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 1458 #define VPEC_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f 1459 #define VPEC_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1460 #define VPEC_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1461 #define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1462 #define VPEC_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1463 #define VPEC_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L 1464 //VPEC_QUEUE3_IB_RPTR 1465 #define VPEC_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 1466 #define VPEC_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1467 //VPEC_QUEUE3_IB_OFFSET 1468 #define VPEC_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 1469 #define VPEC_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1470 //VPEC_QUEUE3_IB_BASE_LO 1471 #define VPEC_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 1472 #define VPEC_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1473 //VPEC_QUEUE3_IB_BASE_HI 1474 #define VPEC_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 1475 #define VPEC_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1476 //VPEC_QUEUE3_IB_SIZE 1477 #define VPEC_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 1478 #define VPEC_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL 1479 //VPEC_QUEUE3_CMDIB_CNTL 1480 #define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1481 #define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1482 #define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1483 #define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1484 #define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 1485 #define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1486 #define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1487 #define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1488 #define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1489 #define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 1490 //VPEC_QUEUE3_CMDIB_RPTR 1491 #define VPEC_QUEUE3_CMDIB_RPTR__OFFSET__SHIFT 0x2 1492 #define VPEC_QUEUE3_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1493 //VPEC_QUEUE3_CMDIB_OFFSET 1494 #define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1495 #define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1496 //VPEC_QUEUE3_CMDIB_BASE_LO 1497 #define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1498 #define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1499 //VPEC_QUEUE3_CMDIB_BASE_HI 1500 #define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1501 #define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1502 //VPEC_QUEUE3_CMDIB_SIZE 1503 #define VPEC_QUEUE3_CMDIB_SIZE__SIZE__SHIFT 0x0 1504 #define VPEC_QUEUE3_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1505 //VPEC_QUEUE3_CSA_ADDR_LO 1506 #define VPEC_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x0 1507 #define VPEC_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1508 //VPEC_QUEUE3_CSA_ADDR_HI 1509 #define VPEC_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 1510 #define VPEC_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1511 //VPEC_QUEUE3_CONTEXT_STATUS 1512 #define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1513 #define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1514 #define VPEC_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 1515 #define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1516 #define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1517 #define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1518 #define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1519 #define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1520 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1521 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1522 #define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1523 #define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1524 #define VPEC_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1525 #define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1526 #define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1527 #define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1528 #define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1529 #define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1530 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1531 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1532 //VPEC_QUEUE3_DOORBELL_LOG 1533 #define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1534 #define VPEC_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 1535 #define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1536 #define VPEC_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1537 //VPEC_QUEUE3_IB_SUB_REMAIN 1538 #define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1539 #define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1540 //VPEC_QUEUE3_PREEMPT 1541 #define VPEC_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 1542 #define VPEC_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1543 //VPEC_QUEUE4_RB_CNTL 1544 #define VPEC_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 1545 #define VPEC_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 1546 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1547 #define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1548 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1549 #define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1550 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1551 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1552 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1553 #define VPEC_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 1554 #define VPEC_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 1555 #define VPEC_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1556 #define VPEC_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1557 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1558 #define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1559 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1560 #define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1561 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1562 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1563 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1564 #define VPEC_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L 1565 #define VPEC_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L 1566 //VPEC_QUEUE4_SCHEDULE_CNTL 1567 #define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1568 #define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1569 #define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1570 #define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1571 #define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1572 #define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1573 #define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1574 #define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1575 //VPEC_QUEUE4_RB_BASE 1576 #define VPEC_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 1577 #define VPEC_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1578 //VPEC_QUEUE4_RB_BASE_HI 1579 #define VPEC_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 1580 #define VPEC_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1581 //VPEC_QUEUE4_RB_RPTR 1582 #define VPEC_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 1583 #define VPEC_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1584 //VPEC_QUEUE4_RB_RPTR_HI 1585 #define VPEC_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 1586 #define VPEC_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1587 //VPEC_QUEUE4_RB_WPTR 1588 #define VPEC_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 1589 #define VPEC_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1590 //VPEC_QUEUE4_RB_WPTR_HI 1591 #define VPEC_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 1592 #define VPEC_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1593 //VPEC_QUEUE4_RB_RPTR_ADDR_HI 1594 #define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1595 #define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1596 //VPEC_QUEUE4_RB_RPTR_ADDR_LO 1597 #define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1598 #define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1599 //VPEC_QUEUE4_RB_AQL_CNTL 1600 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1601 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1602 #define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1603 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1604 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1605 #define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1606 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1607 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1608 #define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1609 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1610 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1611 #define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1612 //VPEC_QUEUE4_MINOR_PTR_UPDATE 1613 #define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1614 #define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1615 //VPEC_QUEUE4_CD_INFO 1616 #define VPEC_QUEUE4_CD_INFO__CD_INFO__SHIFT 0x0 1617 #define VPEC_QUEUE4_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1618 //VPEC_QUEUE4_RB_PREEMPT 1619 #define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1620 #define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1621 //VPEC_QUEUE4_SKIP_CNTL 1622 #define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1623 #define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1624 //VPEC_QUEUE4_DOORBELL 1625 #define VPEC_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c 1626 #define VPEC_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e 1627 #define VPEC_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L 1628 #define VPEC_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L 1629 //VPEC_QUEUE4_DOORBELL_OFFSET 1630 #define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1631 #define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1632 //VPEC_QUEUE4_DUMMY0 1633 #define VPEC_QUEUE4_DUMMY0__DUMMY__SHIFT 0x0 1634 #define VPEC_QUEUE4_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1635 //VPEC_QUEUE4_DUMMY1 1636 #define VPEC_QUEUE4_DUMMY1__VALUE__SHIFT 0x0 1637 #define VPEC_QUEUE4_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1638 //VPEC_QUEUE4_DUMMY2 1639 #define VPEC_QUEUE4_DUMMY2__VALUE__SHIFT 0x0 1640 #define VPEC_QUEUE4_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1641 //VPEC_QUEUE4_DUMMY3 1642 #define VPEC_QUEUE4_DUMMY3__VALUE__SHIFT 0x0 1643 #define VPEC_QUEUE4_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1644 //VPEC_QUEUE4_DUMMY4 1645 #define VPEC_QUEUE4_DUMMY4__VALUE__SHIFT 0x0 1646 #define VPEC_QUEUE4_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1647 //VPEC_QUEUE4_IB_CNTL 1648 #define VPEC_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 1649 #define VPEC_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1650 #define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1651 #define VPEC_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 1652 #define VPEC_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f 1653 #define VPEC_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1654 #define VPEC_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1655 #define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1656 #define VPEC_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1657 #define VPEC_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L 1658 //VPEC_QUEUE4_IB_RPTR 1659 #define VPEC_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 1660 #define VPEC_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1661 //VPEC_QUEUE4_IB_OFFSET 1662 #define VPEC_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 1663 #define VPEC_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1664 //VPEC_QUEUE4_IB_BASE_LO 1665 #define VPEC_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 1666 #define VPEC_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1667 //VPEC_QUEUE4_IB_BASE_HI 1668 #define VPEC_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 1669 #define VPEC_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1670 //VPEC_QUEUE4_IB_SIZE 1671 #define VPEC_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 1672 #define VPEC_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL 1673 //VPEC_QUEUE4_CMDIB_CNTL 1674 #define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1675 #define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1676 #define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1677 #define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1678 #define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 1679 #define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1680 #define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1681 #define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1682 #define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1683 #define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 1684 //VPEC_QUEUE4_CMDIB_RPTR 1685 #define VPEC_QUEUE4_CMDIB_RPTR__OFFSET__SHIFT 0x2 1686 #define VPEC_QUEUE4_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1687 //VPEC_QUEUE4_CMDIB_OFFSET 1688 #define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1689 #define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1690 //VPEC_QUEUE4_CMDIB_BASE_LO 1691 #define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1692 #define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1693 //VPEC_QUEUE4_CMDIB_BASE_HI 1694 #define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1695 #define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1696 //VPEC_QUEUE4_CMDIB_SIZE 1697 #define VPEC_QUEUE4_CMDIB_SIZE__SIZE__SHIFT 0x0 1698 #define VPEC_QUEUE4_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1699 //VPEC_QUEUE4_CSA_ADDR_LO 1700 #define VPEC_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x0 1701 #define VPEC_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1702 //VPEC_QUEUE4_CSA_ADDR_HI 1703 #define VPEC_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 1704 #define VPEC_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1705 //VPEC_QUEUE4_CONTEXT_STATUS 1706 #define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1707 #define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1708 #define VPEC_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 1709 #define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1710 #define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1711 #define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1712 #define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1713 #define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1714 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1715 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1716 #define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1717 #define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1718 #define VPEC_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1719 #define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1720 #define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1721 #define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1722 #define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1723 #define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1724 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1725 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1726 //VPEC_QUEUE4_DOORBELL_LOG 1727 #define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1728 #define VPEC_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 1729 #define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1730 #define VPEC_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1731 //VPEC_QUEUE4_IB_SUB_REMAIN 1732 #define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1733 #define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1734 //VPEC_QUEUE4_PREEMPT 1735 #define VPEC_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 1736 #define VPEC_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1737 //VPEC_QUEUE5_RB_CNTL 1738 #define VPEC_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 1739 #define VPEC_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 1740 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1741 #define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1742 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1743 #define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1744 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1745 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1746 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1747 #define VPEC_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 1748 #define VPEC_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 1749 #define VPEC_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1750 #define VPEC_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1751 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1752 #define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1753 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1754 #define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1755 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1756 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1757 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1758 #define VPEC_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L 1759 #define VPEC_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L 1760 //VPEC_QUEUE5_SCHEDULE_CNTL 1761 #define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1762 #define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1763 #define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1764 #define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1765 #define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1766 #define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1767 #define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1768 #define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1769 //VPEC_QUEUE5_RB_BASE 1770 #define VPEC_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 1771 #define VPEC_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1772 //VPEC_QUEUE5_RB_BASE_HI 1773 #define VPEC_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 1774 #define VPEC_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1775 //VPEC_QUEUE5_RB_RPTR 1776 #define VPEC_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 1777 #define VPEC_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1778 //VPEC_QUEUE5_RB_RPTR_HI 1779 #define VPEC_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 1780 #define VPEC_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1781 //VPEC_QUEUE5_RB_WPTR 1782 #define VPEC_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 1783 #define VPEC_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1784 //VPEC_QUEUE5_RB_WPTR_HI 1785 #define VPEC_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 1786 #define VPEC_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1787 //VPEC_QUEUE5_RB_RPTR_ADDR_HI 1788 #define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1789 #define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1790 //VPEC_QUEUE5_RB_RPTR_ADDR_LO 1791 #define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1792 #define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1793 //VPEC_QUEUE5_RB_AQL_CNTL 1794 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1795 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1796 #define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1797 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1798 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1799 #define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1800 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1801 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1802 #define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1803 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1804 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1805 #define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1806 //VPEC_QUEUE5_MINOR_PTR_UPDATE 1807 #define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1808 #define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1809 //VPEC_QUEUE5_CD_INFO 1810 #define VPEC_QUEUE5_CD_INFO__CD_INFO__SHIFT 0x0 1811 #define VPEC_QUEUE5_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1812 //VPEC_QUEUE5_RB_PREEMPT 1813 #define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1814 #define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1815 //VPEC_QUEUE5_SKIP_CNTL 1816 #define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1817 #define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1818 //VPEC_QUEUE5_DOORBELL 1819 #define VPEC_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c 1820 #define VPEC_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e 1821 #define VPEC_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L 1822 #define VPEC_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L 1823 //VPEC_QUEUE5_DOORBELL_OFFSET 1824 #define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1825 #define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1826 //VPEC_QUEUE5_DUMMY0 1827 #define VPEC_QUEUE5_DUMMY0__DUMMY__SHIFT 0x0 1828 #define VPEC_QUEUE5_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1829 //VPEC_QUEUE5_DUMMY1 1830 #define VPEC_QUEUE5_DUMMY1__VALUE__SHIFT 0x0 1831 #define VPEC_QUEUE5_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1832 //VPEC_QUEUE5_DUMMY2 1833 #define VPEC_QUEUE5_DUMMY2__VALUE__SHIFT 0x0 1834 #define VPEC_QUEUE5_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1835 //VPEC_QUEUE5_DUMMY3 1836 #define VPEC_QUEUE5_DUMMY3__VALUE__SHIFT 0x0 1837 #define VPEC_QUEUE5_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1838 //VPEC_QUEUE5_DUMMY4 1839 #define VPEC_QUEUE5_DUMMY4__VALUE__SHIFT 0x0 1840 #define VPEC_QUEUE5_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1841 //VPEC_QUEUE5_IB_CNTL 1842 #define VPEC_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 1843 #define VPEC_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1844 #define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1845 #define VPEC_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 1846 #define VPEC_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f 1847 #define VPEC_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1848 #define VPEC_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1849 #define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1850 #define VPEC_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1851 #define VPEC_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L 1852 //VPEC_QUEUE5_IB_RPTR 1853 #define VPEC_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 1854 #define VPEC_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1855 //VPEC_QUEUE5_IB_OFFSET 1856 #define VPEC_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 1857 #define VPEC_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1858 //VPEC_QUEUE5_IB_BASE_LO 1859 #define VPEC_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 1860 #define VPEC_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1861 //VPEC_QUEUE5_IB_BASE_HI 1862 #define VPEC_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 1863 #define VPEC_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1864 //VPEC_QUEUE5_IB_SIZE 1865 #define VPEC_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 1866 #define VPEC_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL 1867 //VPEC_QUEUE5_CMDIB_CNTL 1868 #define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1869 #define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1870 #define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1871 #define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1872 #define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 1873 #define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1874 #define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1875 #define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1876 #define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1877 #define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 1878 //VPEC_QUEUE5_CMDIB_RPTR 1879 #define VPEC_QUEUE5_CMDIB_RPTR__OFFSET__SHIFT 0x2 1880 #define VPEC_QUEUE5_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1881 //VPEC_QUEUE5_CMDIB_OFFSET 1882 #define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1883 #define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1884 //VPEC_QUEUE5_CMDIB_BASE_LO 1885 #define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1886 #define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1887 //VPEC_QUEUE5_CMDIB_BASE_HI 1888 #define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1889 #define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1890 //VPEC_QUEUE5_CMDIB_SIZE 1891 #define VPEC_QUEUE5_CMDIB_SIZE__SIZE__SHIFT 0x0 1892 #define VPEC_QUEUE5_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1893 //VPEC_QUEUE5_CSA_ADDR_LO 1894 #define VPEC_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x0 1895 #define VPEC_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1896 //VPEC_QUEUE5_CSA_ADDR_HI 1897 #define VPEC_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 1898 #define VPEC_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1899 //VPEC_QUEUE5_CONTEXT_STATUS 1900 #define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1901 #define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1902 #define VPEC_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 1903 #define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1904 #define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1905 #define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1906 #define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1907 #define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1908 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1909 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1910 #define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1911 #define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1912 #define VPEC_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1913 #define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1914 #define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1915 #define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1916 #define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1917 #define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1918 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1919 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1920 //VPEC_QUEUE5_DOORBELL_LOG 1921 #define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1922 #define VPEC_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 1923 #define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1924 #define VPEC_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1925 //VPEC_QUEUE5_IB_SUB_REMAIN 1926 #define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1927 #define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1928 //VPEC_QUEUE5_PREEMPT 1929 #define VPEC_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 1930 #define VPEC_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1931 //VPEC_QUEUE6_RB_CNTL 1932 #define VPEC_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 1933 #define VPEC_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 1934 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1935 #define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1936 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1937 #define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1938 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1939 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1940 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1941 #define VPEC_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 1942 #define VPEC_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 1943 #define VPEC_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1944 #define VPEC_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1945 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1946 #define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1947 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1948 #define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1949 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1950 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1951 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1952 #define VPEC_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L 1953 #define VPEC_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L 1954 //VPEC_QUEUE6_SCHEDULE_CNTL 1955 #define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1956 #define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1957 #define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1958 #define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1959 #define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1960 #define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1961 #define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1962 #define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1963 //VPEC_QUEUE6_RB_BASE 1964 #define VPEC_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 1965 #define VPEC_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1966 //VPEC_QUEUE6_RB_BASE_HI 1967 #define VPEC_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 1968 #define VPEC_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1969 //VPEC_QUEUE6_RB_RPTR 1970 #define VPEC_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 1971 #define VPEC_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1972 //VPEC_QUEUE6_RB_RPTR_HI 1973 #define VPEC_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 1974 #define VPEC_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1975 //VPEC_QUEUE6_RB_WPTR 1976 #define VPEC_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 1977 #define VPEC_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1978 //VPEC_QUEUE6_RB_WPTR_HI 1979 #define VPEC_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 1980 #define VPEC_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1981 //VPEC_QUEUE6_RB_RPTR_ADDR_HI 1982 #define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1983 #define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1984 //VPEC_QUEUE6_RB_RPTR_ADDR_LO 1985 #define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1986 #define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1987 //VPEC_QUEUE6_RB_AQL_CNTL 1988 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1989 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1990 #define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1991 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1992 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1993 #define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1994 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1995 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1996 #define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1997 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1998 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1999 #define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 2000 //VPEC_QUEUE6_MINOR_PTR_UPDATE 2001 #define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2002 #define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2003 //VPEC_QUEUE6_CD_INFO 2004 #define VPEC_QUEUE6_CD_INFO__CD_INFO__SHIFT 0x0 2005 #define VPEC_QUEUE6_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 2006 //VPEC_QUEUE6_RB_PREEMPT 2007 #define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 2008 #define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 2009 //VPEC_QUEUE6_SKIP_CNTL 2010 #define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2011 #define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2012 //VPEC_QUEUE6_DOORBELL 2013 #define VPEC_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c 2014 #define VPEC_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e 2015 #define VPEC_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L 2016 #define VPEC_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L 2017 //VPEC_QUEUE6_DOORBELL_OFFSET 2018 #define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2019 #define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2020 //VPEC_QUEUE6_DUMMY0 2021 #define VPEC_QUEUE6_DUMMY0__DUMMY__SHIFT 0x0 2022 #define VPEC_QUEUE6_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 2023 //VPEC_QUEUE6_DUMMY1 2024 #define VPEC_QUEUE6_DUMMY1__VALUE__SHIFT 0x0 2025 #define VPEC_QUEUE6_DUMMY1__VALUE_MASK 0xFFFFFFFFL 2026 //VPEC_QUEUE6_DUMMY2 2027 #define VPEC_QUEUE6_DUMMY2__VALUE__SHIFT 0x0 2028 #define VPEC_QUEUE6_DUMMY2__VALUE_MASK 0xFFFFFFFFL 2029 //VPEC_QUEUE6_DUMMY3 2030 #define VPEC_QUEUE6_DUMMY3__VALUE__SHIFT 0x0 2031 #define VPEC_QUEUE6_DUMMY3__VALUE_MASK 0xFFFFFFFFL 2032 //VPEC_QUEUE6_DUMMY4 2033 #define VPEC_QUEUE6_DUMMY4__VALUE__SHIFT 0x0 2034 #define VPEC_QUEUE6_DUMMY4__VALUE_MASK 0xFFFFFFFFL 2035 //VPEC_QUEUE6_IB_CNTL 2036 #define VPEC_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2037 #define VPEC_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2038 #define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2039 #define VPEC_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 2040 #define VPEC_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f 2041 #define VPEC_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2042 #define VPEC_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2043 #define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2044 #define VPEC_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2045 #define VPEC_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L 2046 //VPEC_QUEUE6_IB_RPTR 2047 #define VPEC_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 2048 #define VPEC_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2049 //VPEC_QUEUE6_IB_OFFSET 2050 #define VPEC_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 2051 #define VPEC_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2052 //VPEC_QUEUE6_IB_BASE_LO 2053 #define VPEC_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 2054 #define VPEC_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2055 //VPEC_QUEUE6_IB_BASE_HI 2056 #define VPEC_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 2057 #define VPEC_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2058 //VPEC_QUEUE6_IB_SIZE 2059 #define VPEC_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 2060 #define VPEC_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2061 //VPEC_QUEUE6_CMDIB_CNTL 2062 #define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 2063 #define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2064 #define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2065 #define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 2066 #define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 2067 #define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 2068 #define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2069 #define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2070 #define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 2071 #define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 2072 //VPEC_QUEUE6_CMDIB_RPTR 2073 #define VPEC_QUEUE6_CMDIB_RPTR__OFFSET__SHIFT 0x2 2074 #define VPEC_QUEUE6_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 2075 //VPEC_QUEUE6_CMDIB_OFFSET 2076 #define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET__SHIFT 0x2 2077 #define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 2078 //VPEC_QUEUE6_CMDIB_BASE_LO 2079 #define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR__SHIFT 0x5 2080 #define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2081 //VPEC_QUEUE6_CMDIB_BASE_HI 2082 #define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR__SHIFT 0x0 2083 #define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2084 //VPEC_QUEUE6_CMDIB_SIZE 2085 #define VPEC_QUEUE6_CMDIB_SIZE__SIZE__SHIFT 0x0 2086 #define VPEC_QUEUE6_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 2087 //VPEC_QUEUE6_CSA_ADDR_LO 2088 #define VPEC_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x0 2089 #define VPEC_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 2090 //VPEC_QUEUE6_CSA_ADDR_HI 2091 #define VPEC_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2092 #define VPEC_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2093 //VPEC_QUEUE6_CONTEXT_STATUS 2094 #define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2095 #define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 2096 #define VPEC_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2097 #define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2098 #define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2099 #define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2100 #define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2101 #define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 2102 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 2103 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 2104 #define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2105 #define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 2106 #define VPEC_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2107 #define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2108 #define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2109 #define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2110 #define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2111 #define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 2112 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 2113 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 2114 //VPEC_QUEUE6_DOORBELL_LOG 2115 #define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2116 #define VPEC_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 2117 #define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2118 #define VPEC_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2119 //VPEC_QUEUE6_IB_SUB_REMAIN 2120 #define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2121 #define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 2122 //VPEC_QUEUE6_PREEMPT 2123 #define VPEC_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2124 #define VPEC_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2125 //VPEC_QUEUE7_RB_CNTL 2126 #define VPEC_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2127 #define VPEC_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 2128 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 2129 #define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2130 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 2131 #define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 2132 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2133 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2134 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2135 #define VPEC_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 2136 #define VPEC_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 2137 #define VPEC_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2138 #define VPEC_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2139 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 2140 #define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2141 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 2142 #define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 2143 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2144 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2145 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2146 #define VPEC_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2147 #define VPEC_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2148 //VPEC_QUEUE7_SCHEDULE_CNTL 2149 #define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 2150 #define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 2151 #define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 2152 #define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 2153 #define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 2154 #define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 2155 #define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 2156 #define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 2157 //VPEC_QUEUE7_RB_BASE 2158 #define VPEC_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 2159 #define VPEC_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2160 //VPEC_QUEUE7_RB_BASE_HI 2161 #define VPEC_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 2162 #define VPEC_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2163 //VPEC_QUEUE7_RB_RPTR 2164 #define VPEC_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 2165 #define VPEC_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2166 //VPEC_QUEUE7_RB_RPTR_HI 2167 #define VPEC_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2168 #define VPEC_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2169 //VPEC_QUEUE7_RB_WPTR 2170 #define VPEC_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 2171 #define VPEC_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2172 //VPEC_QUEUE7_RB_WPTR_HI 2173 #define VPEC_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2174 #define VPEC_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2175 //VPEC_QUEUE7_RB_RPTR_ADDR_HI 2176 #define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2177 #define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2178 //VPEC_QUEUE7_RB_RPTR_ADDR_LO 2179 #define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2180 #define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2181 //VPEC_QUEUE7_RB_AQL_CNTL 2182 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2183 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2184 #define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2185 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 2186 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 2187 #define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 2188 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2189 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2190 #define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2191 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 2192 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 2193 #define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 2194 //VPEC_QUEUE7_MINOR_PTR_UPDATE 2195 #define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2196 #define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2197 //VPEC_QUEUE7_CD_INFO 2198 #define VPEC_QUEUE7_CD_INFO__CD_INFO__SHIFT 0x0 2199 #define VPEC_QUEUE7_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 2200 //VPEC_QUEUE7_RB_PREEMPT 2201 #define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 2202 #define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 2203 //VPEC_QUEUE7_SKIP_CNTL 2204 #define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2205 #define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2206 //VPEC_QUEUE7_DOORBELL 2207 #define VPEC_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c 2208 #define VPEC_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e 2209 #define VPEC_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L 2210 #define VPEC_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L 2211 //VPEC_QUEUE7_DOORBELL_OFFSET 2212 #define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2213 #define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2214 //VPEC_QUEUE7_DUMMY0 2215 #define VPEC_QUEUE7_DUMMY0__DUMMY__SHIFT 0x0 2216 #define VPEC_QUEUE7_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 2217 //VPEC_QUEUE7_DUMMY1 2218 #define VPEC_QUEUE7_DUMMY1__VALUE__SHIFT 0x0 2219 #define VPEC_QUEUE7_DUMMY1__VALUE_MASK 0xFFFFFFFFL 2220 //VPEC_QUEUE7_DUMMY2 2221 #define VPEC_QUEUE7_DUMMY2__VALUE__SHIFT 0x0 2222 #define VPEC_QUEUE7_DUMMY2__VALUE_MASK 0xFFFFFFFFL 2223 //VPEC_QUEUE7_DUMMY3 2224 #define VPEC_QUEUE7_DUMMY3__VALUE__SHIFT 0x0 2225 #define VPEC_QUEUE7_DUMMY3__VALUE_MASK 0xFFFFFFFFL 2226 //VPEC_QUEUE7_DUMMY4 2227 #define VPEC_QUEUE7_DUMMY4__VALUE__SHIFT 0x0 2228 #define VPEC_QUEUE7_DUMMY4__VALUE_MASK 0xFFFFFFFFL 2229 //VPEC_QUEUE7_IB_CNTL 2230 #define VPEC_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2231 #define VPEC_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2232 #define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2233 #define VPEC_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 2234 #define VPEC_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f 2235 #define VPEC_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2236 #define VPEC_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2237 #define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2238 #define VPEC_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2239 #define VPEC_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L 2240 //VPEC_QUEUE7_IB_RPTR 2241 #define VPEC_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 2242 #define VPEC_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2243 //VPEC_QUEUE7_IB_OFFSET 2244 #define VPEC_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 2245 #define VPEC_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2246 //VPEC_QUEUE7_IB_BASE_LO 2247 #define VPEC_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 2248 #define VPEC_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2249 //VPEC_QUEUE7_IB_BASE_HI 2250 #define VPEC_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 2251 #define VPEC_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2252 //VPEC_QUEUE7_IB_SIZE 2253 #define VPEC_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 2254 #define VPEC_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2255 //VPEC_QUEUE7_CMDIB_CNTL 2256 #define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 2257 #define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2258 #define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2259 #define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 2260 #define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f 2261 #define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 2262 #define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2263 #define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2264 #define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 2265 #define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L 2266 //VPEC_QUEUE7_CMDIB_RPTR 2267 #define VPEC_QUEUE7_CMDIB_RPTR__OFFSET__SHIFT 0x2 2268 #define VPEC_QUEUE7_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 2269 //VPEC_QUEUE7_CMDIB_OFFSET 2270 #define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET__SHIFT 0x2 2271 #define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 2272 //VPEC_QUEUE7_CMDIB_BASE_LO 2273 #define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR__SHIFT 0x5 2274 #define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2275 //VPEC_QUEUE7_CMDIB_BASE_HI 2276 #define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR__SHIFT 0x0 2277 #define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2278 //VPEC_QUEUE7_CMDIB_SIZE 2279 #define VPEC_QUEUE7_CMDIB_SIZE__SIZE__SHIFT 0x0 2280 #define VPEC_QUEUE7_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 2281 //VPEC_QUEUE7_CSA_ADDR_LO 2282 #define VPEC_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x0 2283 #define VPEC_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 2284 //VPEC_QUEUE7_CSA_ADDR_HI 2285 #define VPEC_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2286 #define VPEC_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2287 //VPEC_QUEUE7_CONTEXT_STATUS 2288 #define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2289 #define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 2290 #define VPEC_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2291 #define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2292 #define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2293 #define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2294 #define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2295 #define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 2296 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 2297 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 2298 #define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2299 #define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 2300 #define VPEC_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2301 #define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2302 #define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2303 #define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2304 #define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2305 #define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 2306 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 2307 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 2308 //VPEC_QUEUE7_DOORBELL_LOG 2309 #define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2310 #define VPEC_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 2311 #define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2312 #define VPEC_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2313 //VPEC_QUEUE7_IB_SUB_REMAIN 2314 #define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2315 #define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 2316 //VPEC_QUEUE7_PREEMPT 2317 #define VPEC_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2318 #define VPEC_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2319 2320 2321 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpcnvc_cfg_dispdec 2322 //VPCNVC_SURFACE_PIXEL_FORMAT 2323 #define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 2324 #define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL 2325 //VPCNVC_FORMAT_CONTROL 2326 #define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 2327 #define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 2328 #define VPCNVC_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 2329 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS__SHIFT 0xc 2330 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN__SHIFT 0xd 2331 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 2332 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 2333 #define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING__SHIFT 0x14 2334 #define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L 2335 #define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L 2336 #define VPCNVC_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L 2337 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MASK 0x00001000L 2338 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L 2339 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L 2340 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L 2341 #define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING_MASK 0x00100000L 2342 //VPCNVC_FCNV_FP_BIAS_R 2343 #define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 2344 #define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL 2345 //VPCNVC_FCNV_FP_BIAS_G 2346 #define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 2347 #define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL 2348 //VPCNVC_FCNV_FP_BIAS_B 2349 #define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 2350 #define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL 2351 //VPCNVC_FCNV_FP_SCALE_R 2352 #define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 2353 #define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL 2354 //VPCNVC_FCNV_FP_SCALE_G 2355 #define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 2356 #define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL 2357 //VPCNVC_FCNV_FP_SCALE_B 2358 #define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 2359 #define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL 2360 //VPCNVC_COLOR_KEYER_CONTROL 2361 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 2362 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 2363 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L 2364 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L 2365 //VPCNVC_COLOR_KEYER_ALPHA 2366 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 2367 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 2368 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL 2369 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L 2370 //VPCNVC_COLOR_KEYER_RED 2371 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 2372 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 2373 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL 2374 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L 2375 //VPCNVC_COLOR_KEYER_GREEN 2376 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 2377 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 2378 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL 2379 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L 2380 //VPCNVC_COLOR_KEYER_BLUE 2381 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 2382 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 2383 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL 2384 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L 2385 //VPCNVC_ALPHA_2BIT_LUT 2386 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 2387 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 2388 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 2389 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 2390 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL 2391 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L 2392 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L 2393 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L 2394 //VPCNVC_PRE_DEALPHA 2395 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 2396 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 2397 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L 2398 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L 2399 //VPCNVC_PRE_CSC_MODE 2400 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 2401 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 2402 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000001L 2403 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x00000004L 2404 //VPCNVC_PRE_CSC_C11_C12 2405 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 2406 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 2407 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL 2408 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L 2409 //VPCNVC_PRE_CSC_C13_C14 2410 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 2411 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 2412 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL 2413 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L 2414 //VPCNVC_PRE_CSC_C21_C22 2415 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 2416 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 2417 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL 2418 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L 2419 //VPCNVC_PRE_CSC_C23_C24 2420 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 2421 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 2422 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL 2423 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L 2424 //VPCNVC_PRE_CSC_C31_C32 2425 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 2426 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 2427 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL 2428 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L 2429 //VPCNVC_PRE_CSC_C33_C34 2430 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 2431 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 2432 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL 2433 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L 2434 //VPCNVC_COEF_FORMAT 2435 #define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 2436 #define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L 2437 //VPCNVC_PRE_DEGAM 2438 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 2439 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 2440 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L 2441 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L 2442 //VPCNVC_PRE_REALPHA 2443 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 2444 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 2445 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L 2446 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L 2447 //VPCNVC_CFG_TEST_DEBUG_INDEX 2448 #define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_INDEX__SHIFT 0x0 2449 #define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 2450 #define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_INDEX_MASK 0x000000FFL 2451 #define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 2452 //VPCNVC_CFG_TEST_DEBUG_DATA 2453 #define VPCNVC_CFG_TEST_DEBUG_DATA__VPCNVC_CFG_TEST_DEBUG_DATA__SHIFT 0x0 2454 #define VPCNVC_CFG_TEST_DEBUG_DATA__VPCNVC_CFG_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 2455 2456 2457 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpdscl_dispdec 2458 //VPDSCL_COEF_RAM_TAP_SELECT 2459 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 2460 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 2461 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 2462 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L 2463 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L 2464 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L 2465 //VPDSCL_COEF_RAM_TAP_DATA 2466 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 2467 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf 2468 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 2469 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f 2470 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL 2471 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L 2472 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L 2473 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L 2474 //VPDSCL_MODE 2475 #define VPDSCL_MODE__VPDSCL_MODE__SHIFT 0x0 2476 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc 2477 #define VPDSCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 2478 #define VPDSCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 2479 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 2480 #define VPDSCL_MODE__VPDSCL_MODE_MASK 0x00000007L 2481 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L 2482 #define VPDSCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L 2483 #define VPDSCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L 2484 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L 2485 //VPDSCL_TAP_CONTROL 2486 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 2487 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 2488 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 2489 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc 2490 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L 2491 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L 2492 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L 2493 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L 2494 //VPDSCL_CONTROL 2495 #define VPDSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 2496 #define VPDSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L 2497 //VPDSCL_2TAP_CONTROL 2498 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 2499 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 2500 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 2501 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 2502 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 2503 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 2504 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L 2505 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L 2506 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L 2507 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L 2508 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L 2509 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L 2510 //VPDSCL_MANUAL_REPLICATE_CONTROL 2511 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 2512 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 2513 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL 2514 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L 2515 //VPDSCL_HORZ_FILTER_SCALE_RATIO 2516 #define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 2517 #define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL 2518 //VPDSCL_HORZ_FILTER_INIT 2519 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 2520 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 2521 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL 2522 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L 2523 //VPDSCL_HORZ_FILTER_SCALE_RATIO_C 2524 #define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 2525 #define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL 2526 //VPDSCL_HORZ_FILTER_INIT_C 2527 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 2528 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 2529 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL 2530 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L 2531 //VPDSCL_VERT_FILTER_SCALE_RATIO 2532 #define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 2533 #define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL 2534 //VPDSCL_VERT_FILTER_INIT 2535 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 2536 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 2537 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL 2538 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L 2539 //VPDSCL_VERT_FILTER_INIT_BOT 2540 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 2541 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 2542 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL 2543 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L 2544 //VPDSCL_VERT_FILTER_SCALE_RATIO_C 2545 #define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 2546 #define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL 2547 //VPDSCL_VERT_FILTER_INIT_C 2548 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 2549 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 2550 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL 2551 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L 2552 //VPDSCL_VERT_FILTER_INIT_BOT_C 2553 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 2554 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 2555 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL 2556 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L 2557 //VPDSCL_BLACK_COLOR 2558 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 2559 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 2560 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL 2561 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L 2562 //VPDSCL_UPDATE 2563 #define VPDSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 2564 #define VPDSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L 2565 //VPDSCL_AUTOCAL 2566 #define VPDSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 2567 #define VPDSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L 2568 //VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 2569 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 2570 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 2571 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL 2572 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L 2573 //VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 2574 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 2575 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 2576 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL 2577 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L 2578 //VPOTG_H_BLANK 2579 #define VPOTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 2580 #define VPOTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 2581 #define VPOTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL 2582 #define VPOTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L 2583 //VPOTG_V_BLANK 2584 #define VPOTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 2585 #define VPOTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 2586 #define VPOTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL 2587 #define VPOTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L 2588 //VPDSCL_RECOUT_START 2589 #define VPDSCL_RECOUT_START__RECOUT_START_X__SHIFT 0x0 2590 #define VPDSCL_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 2591 #define VPDSCL_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL 2592 #define VPDSCL_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L 2593 //VPDSCL_RECOUT_SIZE 2594 #define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 2595 #define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 2596 #define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL 2597 #define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L 2598 //VPMPC_SIZE 2599 #define VPMPC_SIZE__VPMPC_WIDTH__SHIFT 0x0 2600 #define VPMPC_SIZE__VPMPC_HEIGHT__SHIFT 0x10 2601 #define VPMPC_SIZE__VPMPC_WIDTH_MASK 0x00003FFFL 2602 #define VPMPC_SIZE__VPMPC_HEIGHT_MASK 0x3FFF0000L 2603 //VPLB_DATA_FORMAT 2604 #define VPLB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 2605 #define VPLB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L 2606 //VPLB_MEMORY_CTRL 2607 #define VPLB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 2608 #define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 2609 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 2610 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 2611 #define VPLB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L 2612 #define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L 2613 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L 2614 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L 2615 //VPLB_V_COUNTER 2616 #define VPLB_V_COUNTER__V_COUNTER__SHIFT 0x0 2617 #define VPLB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 2618 #define VPLB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL 2619 #define VPLB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L 2620 //VPDSCL_MEM_PWR_CTRL 2621 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 2622 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 2623 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 2624 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 2625 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 2626 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa 2627 #define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c 2628 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L 2629 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L 2630 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L 2631 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L 2632 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L 2633 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L 2634 #define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L 2635 //VPDSCL_MEM_PWR_STATUS 2636 #define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 2637 #define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 2638 #define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 2639 #define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L 2640 #define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL 2641 #define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L 2642 //VPDSCL_DEBUG 2643 #define VPDSCL_DEBUG__SCL_DEBUG__SHIFT 0x0 2644 #define VPDSCL_DEBUG__SCL_DEBUG_MASK 0xFFFFFFFFL 2645 //VPDSCL_TEST_DEBUG_INDEX 2646 #define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 2647 #define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 2648 #define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000FFL 2649 #define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 2650 //VPDSCL_TEST_DEBUG_DATA 2651 #define VPDSCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 2652 #define VPDSCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 2653 2654 2655 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpcm_dispdec 2656 //VPCM_CONTROL 2657 #define VPCM_CONTROL__VPCM_BYPASS__SHIFT 0x0 2658 #define VPCM_CONTROL__VPCM_UPDATE_PENDING__SHIFT 0x8 2659 #define VPCM_CONTROL__VPCM_BYPASS_MASK 0x00000001L 2660 #define VPCM_CONTROL__VPCM_UPDATE_PENDING_MASK 0x00000100L 2661 //VPCM_POST_CSC_CONTROL 2662 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE__SHIFT 0x0 2663 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT__SHIFT 0x2 2664 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_MASK 0x00000001L 2665 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT_MASK 0x00000004L 2666 //VPCM_POST_CSC_C11_C12 2667 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11__SHIFT 0x0 2668 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12__SHIFT 0x10 2669 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11_MASK 0x0000FFFFL 2670 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12_MASK 0xFFFF0000L 2671 //VPCM_POST_CSC_C13_C14 2672 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13__SHIFT 0x0 2673 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14__SHIFT 0x10 2674 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13_MASK 0x0000FFFFL 2675 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14_MASK 0xFFFF0000L 2676 //VPCM_POST_CSC_C21_C22 2677 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21__SHIFT 0x0 2678 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22__SHIFT 0x10 2679 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21_MASK 0x0000FFFFL 2680 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22_MASK 0xFFFF0000L 2681 //VPCM_POST_CSC_C23_C24 2682 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23__SHIFT 0x0 2683 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24__SHIFT 0x10 2684 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23_MASK 0x0000FFFFL 2685 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24_MASK 0xFFFF0000L 2686 //VPCM_POST_CSC_C31_C32 2687 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31__SHIFT 0x0 2688 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32__SHIFT 0x10 2689 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31_MASK 0x0000FFFFL 2690 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32_MASK 0xFFFF0000L 2691 //VPCM_POST_CSC_C33_C34 2692 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33__SHIFT 0x0 2693 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34__SHIFT 0x10 2694 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33_MASK 0x0000FFFFL 2695 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34_MASK 0xFFFF0000L 2696 //VPCM_GAMUT_REMAP_CONTROL 2697 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE__SHIFT 0x0 2698 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 2699 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_MASK 0x00000001L 2700 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000004L 2701 //VPCM_GAMUT_REMAP_C11_C12 2702 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C11__SHIFT 0x0 2703 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C12__SHIFT 0x10 2704 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C11_MASK 0x0000FFFFL 2705 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C12_MASK 0xFFFF0000L 2706 //VPCM_GAMUT_REMAP_C13_C14 2707 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C13__SHIFT 0x0 2708 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C14__SHIFT 0x10 2709 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C13_MASK 0x0000FFFFL 2710 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C14_MASK 0xFFFF0000L 2711 //VPCM_GAMUT_REMAP_C21_C22 2712 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C21__SHIFT 0x0 2713 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C22__SHIFT 0x10 2714 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C21_MASK 0x0000FFFFL 2715 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C22_MASK 0xFFFF0000L 2716 //VPCM_GAMUT_REMAP_C23_C24 2717 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C23__SHIFT 0x0 2718 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C24__SHIFT 0x10 2719 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C23_MASK 0x0000FFFFL 2720 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C24_MASK 0xFFFF0000L 2721 //VPCM_GAMUT_REMAP_C31_C32 2722 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C31__SHIFT 0x0 2723 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C32__SHIFT 0x10 2724 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C31_MASK 0x0000FFFFL 2725 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C32_MASK 0xFFFF0000L 2726 //VPCM_GAMUT_REMAP_C33_C34 2727 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C33__SHIFT 0x0 2728 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C34__SHIFT 0x10 2729 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C33_MASK 0x0000FFFFL 2730 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C34_MASK 0xFFFF0000L 2731 //VPCM_BIAS_CR_R 2732 #define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R__SHIFT 0x0 2733 #define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R_MASK 0x0000FFFFL 2734 //VPCM_BIAS_Y_G_CB_B 2735 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G__SHIFT 0x0 2736 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B__SHIFT 0x10 2737 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G_MASK 0x0000FFFFL 2738 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B_MASK 0xFFFF0000L 2739 //VPCM_GAMCOR_CONTROL 2740 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE__SHIFT 0x0 2741 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE__SHIFT 0x3 2742 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT__SHIFT 0x4 2743 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 2744 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_MASK 0x00000003L 2745 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE_MASK 0x00000008L 2746 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT_MASK 0x00000030L 2747 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L 2748 //VPCM_GAMCOR_LUT_INDEX 2749 #define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX__SHIFT 0x0 2750 #define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX_MASK 0x000001FFL 2751 //VPCM_GAMCOR_LUT_DATA 2752 #define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA__SHIFT 0x0 2753 #define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL 2754 //VPCM_GAMCOR_LUT_CONTROL 2755 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 2756 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 2757 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 2758 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 2759 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 2760 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L 2761 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L 2762 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L 2763 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L 2764 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L 2765 //VPCM_GAMCOR_RAMA_START_CNTL_B 2766 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 2767 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 2768 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 2769 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 2770 //VPCM_GAMCOR_RAMA_START_CNTL_G 2771 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 2772 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 2773 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 2774 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 2775 //VPCM_GAMCOR_RAMA_START_CNTL_R 2776 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 2777 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 2778 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 2779 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 2780 //VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 2781 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 2782 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL 2783 //VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 2784 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 2785 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL 2786 //VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 2787 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 2788 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL 2789 //VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 2790 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 2791 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL 2792 //VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 2793 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 2794 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL 2795 //VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 2796 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 2797 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL 2798 //VPCM_GAMCOR_RAMA_END_CNTL1_B 2799 #define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 2800 #define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL 2801 //VPCM_GAMCOR_RAMA_END_CNTL2_B 2802 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 2803 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 2804 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 2805 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L 2806 //VPCM_GAMCOR_RAMA_END_CNTL1_G 2807 #define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 2808 #define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL 2809 //VPCM_GAMCOR_RAMA_END_CNTL2_G 2810 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 2811 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 2812 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 2813 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L 2814 //VPCM_GAMCOR_RAMA_END_CNTL1_R 2815 #define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 2816 #define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL 2817 //VPCM_GAMCOR_RAMA_END_CNTL2_R 2818 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 2819 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 2820 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 2821 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L 2822 //VPCM_GAMCOR_RAMA_OFFSET_B 2823 #define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 2824 #define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL 2825 //VPCM_GAMCOR_RAMA_OFFSET_G 2826 #define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 2827 #define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL 2828 //VPCM_GAMCOR_RAMA_OFFSET_R 2829 #define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 2830 #define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL 2831 //VPCM_GAMCOR_RAMA_REGION_0_1 2832 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 2833 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 2834 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 2835 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 2836 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 2837 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 2838 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 2839 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 2840 //VPCM_GAMCOR_RAMA_REGION_2_3 2841 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 2842 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 2843 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 2844 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 2845 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 2846 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 2847 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 2848 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 2849 //VPCM_GAMCOR_RAMA_REGION_4_5 2850 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 2851 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 2852 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 2853 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 2854 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 2855 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 2856 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 2857 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 2858 //VPCM_GAMCOR_RAMA_REGION_6_7 2859 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 2860 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 2861 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 2862 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 2863 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 2864 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 2865 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 2866 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 2867 //VPCM_GAMCOR_RAMA_REGION_8_9 2868 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 2869 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 2870 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 2871 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 2872 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 2873 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 2874 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 2875 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 2876 //VPCM_GAMCOR_RAMA_REGION_10_11 2877 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 2878 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 2879 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 2880 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 2881 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 2882 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 2883 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 2884 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 2885 //VPCM_GAMCOR_RAMA_REGION_12_13 2886 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 2887 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 2888 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 2889 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 2890 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 2891 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 2892 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 2893 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 2894 //VPCM_GAMCOR_RAMA_REGION_14_15 2895 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 2896 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 2897 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 2898 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 2899 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 2900 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 2901 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 2902 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 2903 //VPCM_GAMCOR_RAMA_REGION_16_17 2904 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 2905 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 2906 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 2907 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 2908 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 2909 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 2910 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 2911 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 2912 //VPCM_GAMCOR_RAMA_REGION_18_19 2913 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 2914 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 2915 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 2916 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 2917 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 2918 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 2919 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 2920 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 2921 //VPCM_GAMCOR_RAMA_REGION_20_21 2922 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 2923 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 2924 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 2925 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 2926 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 2927 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 2928 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 2929 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 2930 //VPCM_GAMCOR_RAMA_REGION_22_23 2931 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 2932 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 2933 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 2934 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 2935 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 2936 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 2937 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 2938 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 2939 //VPCM_GAMCOR_RAMA_REGION_24_25 2940 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 2941 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 2942 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 2943 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 2944 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 2945 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 2946 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 2947 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 2948 //VPCM_GAMCOR_RAMA_REGION_26_27 2949 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 2950 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 2951 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 2952 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 2953 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 2954 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 2955 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 2956 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 2957 //VPCM_GAMCOR_RAMA_REGION_28_29 2958 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 2959 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 2960 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 2961 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 2962 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 2963 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 2964 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 2965 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 2966 //VPCM_GAMCOR_RAMA_REGION_30_31 2967 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 2968 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 2969 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 2970 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 2971 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 2972 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 2973 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 2974 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 2975 //VPCM_GAMCOR_RAMA_REGION_32_33 2976 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 2977 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 2978 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 2979 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 2980 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 2981 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 2982 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 2983 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 2984 //VPCM_HDR_MULT_COEF 2985 #define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF__SHIFT 0x0 2986 #define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF_MASK 0x0007FFFFL 2987 //VPCM_MEM_PWR_CTRL 2988 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 2989 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 2990 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L 2991 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L 2992 //VPCM_MEM_PWR_STATUS 2993 #define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 2994 #define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L 2995 //VPCM_DEALPHA 2996 #define VPCM_DEALPHA__VPCM_DEALPHA_EN__SHIFT 0x0 2997 #define VPCM_DEALPHA__VPCM_DEALPHA_ABLND__SHIFT 0x1 2998 #define VPCM_DEALPHA__VPCM_DEALPHA_EN_MASK 0x00000001L 2999 #define VPCM_DEALPHA__VPCM_DEALPHA_ABLND_MASK 0x00000002L 3000 //VPCM_COEF_FORMAT 3001 #define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT__SHIFT 0x0 3002 #define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT__SHIFT 0x4 3003 #define VPCM_COEF_FORMAT__VPCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 3004 #define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT_MASK 0x00000001L 3005 #define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT_MASK 0x00000010L 3006 #define VPCM_COEF_FORMAT__VPCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L 3007 //VPCM_TEST_DEBUG_INDEX 3008 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX__SHIFT 0x0 3009 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 3010 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX_MASK 0x000000FFL 3011 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3012 //VPCM_TEST_DEBUG_DATA 3013 #define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA__SHIFT 0x0 3014 #define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 3015 3016 3017 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpdpp_top_dispdec 3018 //VPDPP_CONTROL 3019 #define VPDPP_CONTROL__VPDPP_CLOCK_ENABLE__SHIFT 0x4 3020 #define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE__SHIFT 0x8 3021 #define VPDPP_CONTROL__VPECLK_G_DYN_GATE_DISABLE__SHIFT 0xa 3022 #define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE__SHIFT 0xc 3023 #define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0xe 3024 #define VPDPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 3025 #define VPDPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 3026 #define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS__SHIFT 0x18 3027 #define VPDPP_CONTROL__VPDPP_TEST_CLK_SEL__SHIFT 0x1c 3028 #define VPDPP_CONTROL__VPDPP_CLOCK_ENABLE_MASK 0x00000010L 3029 #define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE_MASK 0x00000100L 3030 #define VPDPP_CONTROL__VPECLK_G_DYN_GATE_DISABLE_MASK 0x00000400L 3031 #define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE_MASK 0x00001000L 3032 #define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00004000L 3033 #define VPDPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L 3034 #define VPDPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L 3035 #define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS_MASK 0x01000000L 3036 #define VPDPP_CONTROL__VPDPP_TEST_CLK_SEL_MASK 0x70000000L 3037 //VPDPP_SOFT_RESET 3038 #define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET__SHIFT 0x0 3039 #define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET__SHIFT 0x4 3040 #define VPDPP_SOFT_RESET__VPCM_SOFT_RESET__SHIFT 0x8 3041 #define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET__SHIFT 0xc 3042 #define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET_MASK 0x00000001L 3043 #define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET_MASK 0x00000010L 3044 #define VPDPP_SOFT_RESET__VPCM_SOFT_RESET_MASK 0x00000100L 3045 #define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET_MASK 0x00001000L 3046 //VPDPP_CRC_VAL_R_G 3047 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR__SHIFT 0x0 3048 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y__SHIFT 0x10 3049 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR_MASK 0x0000FFFFL 3050 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y_MASK 0xFFFF0000L 3051 //VPDPP_CRC_VAL_B_A 3052 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB__SHIFT 0x0 3053 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA__SHIFT 0x10 3054 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB_MASK 0x0000FFFFL 3055 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA_MASK 0xFFFF0000L 3056 //VPDPP_CRC_CTRL 3057 #define VPDPP_CRC_CTRL__VPDPP_CRC_EN__SHIFT 0x0 3058 #define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN__SHIFT 0x1 3059 #define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 3060 #define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL__SHIFT 0x3 3061 #define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL__SHIFT 0x4 3062 #define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb 3063 #define VPDPP_CRC_CTRL__VPDPP_CRC_MASK__SHIFT 0x10 3064 #define VPDPP_CRC_CTRL__VPDPP_CRC_EN_MASK 0x00000001L 3065 #define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN_MASK 0x00000002L 3066 #define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L 3067 #define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL_MASK 0x00000008L 3068 #define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL_MASK 0x00000030L 3069 #define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L 3070 #define VPDPP_CRC_CTRL__VPDPP_CRC_MASK_MASK 0xFFFF0000L 3071 //VPHOST_READ_CONTROL 3072 #define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 3073 #define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL 3074 //VPDPP_DEBUG_SEL 3075 #define VPDPP_DEBUG_SEL__VPDPP_VPECLK_DEBUG_BUS_SEL__SHIFT 0x0 3076 #define VPDPP_DEBUG_SEL__VPDPP_DBG_EN__SHIFT 0x1f 3077 #define VPDPP_DEBUG_SEL__VPDPP_VPECLK_DEBUG_BUS_SEL_MASK 0x00000007L 3078 #define VPDPP_DEBUG_SEL__VPDPP_DBG_EN_MASK 0x80000000L 3079 //VPDPP_DEBUG_SPARE 3080 #define VPDPP_DEBUG_SPARE__VPDPP_DEBUG_SPARE__SHIFT 0x0 3081 #define VPDPP_DEBUG_SPARE__VPDPP_DEBUG_SPARE_MASK 0xFFFFFFFFL 3082 //VPDPP_TEST_DEBUG_INDEX 3083 #define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_INDEX__SHIFT 0x0 3084 #define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 3085 #define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_INDEX_MASK 0x000000FFL 3086 #define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3087 //VPDPP_TEST_DEBUG_DATA 3088 #define VPDPP_TEST_DEBUG_DATA__VPDPP_TEST_DEBUG_DATA__SHIFT 0x0 3089 #define VPDPP_TEST_DEBUG_DATA__VPDPP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 3090 3091 3092 // addressBlock: vpe_vpep_vpmpc_vpmpcc0_dispdec 3093 //VPMPCC_TOP_SEL 3094 #define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL__SHIFT 0x0 3095 #define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL_MASK 0x0000000FL 3096 //VPMPCC_BOT_SEL 3097 #define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL__SHIFT 0x0 3098 #define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL_MASK 0x0000000FL 3099 //VPMPCC_VPOPP_ID 3100 #define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID__SHIFT 0x0 3101 #define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID_MASK 0x0000000FL 3102 //VPMPCC_CONTROL 3103 #define VPMPCC_CONTROL__VPMPCC_MODE__SHIFT 0x0 3104 #define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE__SHIFT 0x4 3105 #define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 3106 #define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 3107 #define VPMPCC_CONTROL__VPMPCC_BG_BPC__SHIFT 0x8 3108 #define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE__SHIFT 0xb 3109 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_ALPHA__SHIFT 0x10 3110 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_GAIN__SHIFT 0x18 3111 #define VPMPCC_CONTROL__VPMPCC_MODE_MASK 0x00000003L 3112 #define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE_MASK 0x00000030L 3113 #define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L 3114 #define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L 3115 #define VPMPCC_CONTROL__VPMPCC_BG_BPC_MASK 0x00000700L 3116 #define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE_MASK 0x00000800L 3117 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_ALPHA_MASK 0x00FF0000L 3118 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_GAIN_MASK 0xFF000000L 3119 //VPMPCC_TOP_GAIN 3120 #define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN__SHIFT 0x0 3121 #define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN_MASK 0x0007FFFFL 3122 //VPMPCC_BOT_GAIN_INSIDE 3123 #define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE__SHIFT 0x0 3124 #define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL 3125 //VPMPCC_BOT_GAIN_OUTSIDE 3126 #define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 3127 #define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL 3128 //VPMPCC_MOVABLE_CM_LOCATION_CONTROL 3129 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 3130 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 3131 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L 3132 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L 3133 //VPMPCC_BG_R_CR 3134 #define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR__SHIFT 0x0 3135 #define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR_MASK 0x00000FFFL 3136 //VPMPCC_BG_G_Y 3137 #define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y__SHIFT 0x0 3138 #define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y_MASK 0x00000FFFL 3139 //VPMPCC_BG_B_CB 3140 #define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB__SHIFT 0x0 3141 #define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB_MASK 0x00000FFFL 3142 //VPMPCC_MEM_PWR_CTRL 3143 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 3144 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 3145 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 3146 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 3147 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L 3148 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L 3149 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L 3150 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L 3151 //VPMPCC_STATUS 3152 #define VPMPCC_STATUS__VPMPCC_IDLE__SHIFT 0x0 3153 #define VPMPCC_STATUS__VPMPCC_BUSY__SHIFT 0x1 3154 #define VPMPCC_STATUS__VPMPCC_DISABLED__SHIFT 0x2 3155 #define VPMPCC_STATUS__VPMPCC_IDLE_MASK 0x00000001L 3156 #define VPMPCC_STATUS__VPMPCC_BUSY_MASK 0x00000002L 3157 #define VPMPCC_STATUS__VPMPCC_DISABLED_MASK 0x00000004L 3158 //VPMPCC_TEST_DEBUG_INDEX 3159 #define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_INDEX__SHIFT 0x0 3160 #define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 3161 #define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_INDEX_MASK 0x000000FFL 3162 #define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3163 //VPMPCC_TEST_DEBUG_DATA 3164 #define VPMPCC_TEST_DEBUG_DATA__VPMPCC_TEST_DEBUG_DATA__SHIFT 0x0 3165 #define VPMPCC_TEST_DEBUG_DATA__VPMPCC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 3166 3167 3168 // addressBlock: vpe_vpep_vpmpc_vpmpc_cfg_dispdec 3169 //VPMPC_CLOCK_CONTROL 3170 #define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0x1 3171 #define VPMPC_CLOCK_CONTROL__VPMPC_TEST_CLK_SEL__SHIFT 0x4 3172 #define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00000002L 3173 #define VPMPC_CLOCK_CONTROL__VPMPC_TEST_CLK_SEL_MASK 0x00000030L 3174 //VPMPC_SOFT_RESET 3175 #define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET__SHIFT 0x0 3176 #define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET__SHIFT 0xa 3177 #define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET__SHIFT 0x14 3178 #define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET__SHIFT 0x1f 3179 #define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET_MASK 0x00000001L 3180 #define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET_MASK 0x00000400L 3181 #define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET_MASK 0x00100000L 3182 #define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET_MASK 0x80000000L 3183 //VPMPC_CRC_CTRL 3184 #define VPMPC_CRC_CTRL__VPMPC_CRC_EN__SHIFT 0x0 3185 #define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN__SHIFT 0x4 3186 #define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL__SHIFT 0x18 3187 #define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c 3188 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED__SHIFT 0x1e 3189 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK__SHIFT 0x1f 3190 #define VPMPC_CRC_CTRL__VPMPC_CRC_EN_MASK 0x00000001L 3191 #define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN_MASK 0x00000010L 3192 #define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL_MASK 0x03000000L 3193 #define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L 3194 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED_MASK 0x40000000L 3195 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK_MASK 0x80000000L 3196 //VPMPC_CRC_SEL_CONTROL 3197 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL__SHIFT 0x0 3198 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL__SHIFT 0x4 3199 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK__SHIFT 0x10 3200 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL_MASK 0x0000000FL 3201 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL_MASK 0x000000F0L 3202 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK_MASK 0xFFFF0000L 3203 //VPMPC_CRC_RESULT_AR 3204 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A__SHIFT 0x0 3205 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R__SHIFT 0x10 3206 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A_MASK 0x0000FFFFL 3207 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R_MASK 0xFFFF0000L 3208 //VPMPC_CRC_RESULT_GB 3209 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G__SHIFT 0x0 3210 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B__SHIFT 0x10 3211 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G_MASK 0x0000FFFFL 3212 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B_MASK 0xFFFF0000L 3213 //VPMPC_CRC_RESULT_C 3214 #define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C__SHIFT 0x0 3215 #define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C_MASK 0x0000FFFFL 3216 //VPMPC_DEBUG_CONTROL 3217 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_EN__SHIFT 0x0 3218 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_TOP_DATA_SELECT__SHIFT 0x1 3219 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SELECT__SHIFT 0x4 3220 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFR_SELECT__SHIFT 0x8 3221 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFT_SELECT__SHIFT 0xc 3222 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_EN_MASK 0x00000001L 3223 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_TOP_DATA_SELECT_MASK 0x00000006L 3224 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SELECT_MASK 0x00000070L 3225 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFR_SELECT_MASK 0x00000F00L 3226 #define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFT_SELECT_MASK 0x0000F000L 3227 //VPMPCC_DEBUG_DATA_SELECT 3228 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT0__SHIFT 0x0 3229 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT0__SHIFT 0x4 3230 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT0__SHIFT 0x6 3231 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT1__SHIFT 0x8 3232 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT1__SHIFT 0xc 3233 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT1__SHIFT 0xe 3234 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT2__SHIFT 0x10 3235 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT2__SHIFT 0x14 3236 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT2__SHIFT 0x16 3237 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT3__SHIFT 0x18 3238 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT3__SHIFT 0x1c 3239 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT3__SHIFT 0x1e 3240 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT0_MASK 0x0000000FL 3241 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT0_MASK 0x00000030L 3242 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT0_MASK 0x000000C0L 3243 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT1_MASK 0x00000F00L 3244 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT1_MASK 0x00003000L 3245 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT1_MASK 0x0000C000L 3246 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT2_MASK 0x000F0000L 3247 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT2_MASK 0x00300000L 3248 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT2_MASK 0x00C00000L 3249 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT3_MASK 0x0F000000L 3250 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT3_MASK 0x30000000L 3251 #define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT3_MASK 0xC0000000L 3252 //VPMPC_BYPASS_BG_AR 3253 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA__SHIFT 0x0 3254 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR__SHIFT 0x10 3255 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL 3256 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L 3257 //VPMPC_BYPASS_BG_GB 3258 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y__SHIFT 0x0 3259 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB__SHIFT 0x10 3260 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL 3261 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L 3262 //VPMPC_HOST_READ_CONTROL 3263 #define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 3264 #define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL 3265 //VPMPC_PENDING_STATUS_MISC 3266 #define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 3267 #define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L 3268 //VPMPC_CFG_TEST_DEBUG_INDEX 3269 #define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_INDEX__SHIFT 0x0 3270 #define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 3271 #define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_INDEX_MASK 0x000000FFL 3272 #define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3273 //VPMPC_CFG_TEST_DEBUG_DATA 3274 #define VPMPC_CFG_TEST_DEBUG_DATA__VPMPC_CFG_TEST_DEBUG_DATA__SHIFT 0x0 3275 #define VPMPC_CFG_TEST_DEBUG_DATA__VPMPC_CFG_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 3276 3277 3278 // addressBlock: vpe_vpep_vpmpc_vpmpcc_ogam0_dispdec 3279 //VPMPCC_OGAM_CONTROL 3280 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE__SHIFT 0x0 3281 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE__SHIFT 0x3 3282 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT__SHIFT 0x7 3283 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 3284 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_MASK 0x00000003L 3285 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE_MASK 0x00000008L 3286 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT_MASK 0x00000180L 3287 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L 3288 //VPMPCC_OGAM_LUT_INDEX 3289 #define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX__SHIFT 0x0 3290 #define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX_MASK 0x000001FFL 3291 //VPMPCC_OGAM_LUT_DATA 3292 #define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA__SHIFT 0x0 3293 #define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL 3294 //VPMPCC_OGAM_LUT_CONTROL 3295 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 3296 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 3297 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 3298 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 3299 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 3300 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L 3301 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L 3302 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L 3303 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L 3304 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L 3305 //VPMPCC_OGAM_RAMA_START_CNTL_B 3306 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 3307 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 3308 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 3309 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 3310 //VPMPCC_OGAM_RAMA_START_CNTL_G 3311 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 3312 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 3313 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 3314 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 3315 //VPMPCC_OGAM_RAMA_START_CNTL_R 3316 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 3317 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 3318 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 3319 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 3320 //VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 3321 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 3322 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL 3323 //VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 3324 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 3325 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL 3326 //VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 3327 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 3328 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL 3329 //VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 3330 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 3331 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL 3332 //VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 3333 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 3334 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL 3335 //VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 3336 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 3337 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL 3338 //VPMPCC_OGAM_RAMA_END_CNTL1_B 3339 #define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 3340 #define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL 3341 //VPMPCC_OGAM_RAMA_END_CNTL2_B 3342 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 3343 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 3344 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 3345 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L 3346 //VPMPCC_OGAM_RAMA_END_CNTL1_G 3347 #define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 3348 #define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL 3349 //VPMPCC_OGAM_RAMA_END_CNTL2_G 3350 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 3351 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 3352 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 3353 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L 3354 //VPMPCC_OGAM_RAMA_END_CNTL1_R 3355 #define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 3356 #define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL 3357 //VPMPCC_OGAM_RAMA_END_CNTL2_R 3358 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 3359 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 3360 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 3361 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L 3362 //VPMPCC_OGAM_RAMA_OFFSET_B 3363 #define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 3364 #define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL 3365 //VPMPCC_OGAM_RAMA_OFFSET_G 3366 #define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 3367 #define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL 3368 //VPMPCC_OGAM_RAMA_OFFSET_R 3369 #define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 3370 #define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL 3371 //VPMPCC_OGAM_RAMA_REGION_0_1 3372 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 3373 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 3374 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 3375 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 3376 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 3377 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 3378 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 3379 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 3380 //VPMPCC_OGAM_RAMA_REGION_2_3 3381 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 3382 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 3383 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 3384 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 3385 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 3386 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 3387 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 3388 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 3389 //VPMPCC_OGAM_RAMA_REGION_4_5 3390 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 3391 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 3392 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 3393 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 3394 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 3395 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 3396 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 3397 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 3398 //VPMPCC_OGAM_RAMA_REGION_6_7 3399 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 3400 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 3401 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 3402 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 3403 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 3404 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 3405 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 3406 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 3407 //VPMPCC_OGAM_RAMA_REGION_8_9 3408 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 3409 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 3410 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 3411 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 3412 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 3413 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 3414 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 3415 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 3416 //VPMPCC_OGAM_RAMA_REGION_10_11 3417 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 3418 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 3419 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 3420 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 3421 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 3422 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 3423 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 3424 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 3425 //VPMPCC_OGAM_RAMA_REGION_12_13 3426 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 3427 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 3428 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 3429 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 3430 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 3431 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 3432 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 3433 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 3434 //VPMPCC_OGAM_RAMA_REGION_14_15 3435 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 3436 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 3437 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 3438 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 3439 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 3440 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 3441 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 3442 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 3443 //VPMPCC_OGAM_RAMA_REGION_16_17 3444 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 3445 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 3446 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 3447 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 3448 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 3449 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 3450 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 3451 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 3452 //VPMPCC_OGAM_RAMA_REGION_18_19 3453 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 3454 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 3455 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 3456 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 3457 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 3458 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 3459 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 3460 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 3461 //VPMPCC_OGAM_RAMA_REGION_20_21 3462 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 3463 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 3464 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 3465 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 3466 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 3467 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 3468 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 3469 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 3470 //VPMPCC_OGAM_RAMA_REGION_22_23 3471 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 3472 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 3473 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 3474 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 3475 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 3476 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 3477 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 3478 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 3479 //VPMPCC_OGAM_RAMA_REGION_24_25 3480 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 3481 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 3482 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 3483 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 3484 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 3485 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 3486 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 3487 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 3488 //VPMPCC_OGAM_RAMA_REGION_26_27 3489 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 3490 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 3491 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 3492 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 3493 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 3494 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 3495 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 3496 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 3497 //VPMPCC_OGAM_RAMA_REGION_28_29 3498 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 3499 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 3500 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 3501 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 3502 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 3503 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 3504 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 3505 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 3506 //VPMPCC_OGAM_RAMA_REGION_30_31 3507 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 3508 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 3509 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 3510 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 3511 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 3512 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 3513 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 3514 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 3515 //VPMPCC_OGAM_RAMA_REGION_32_33 3516 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 3517 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 3518 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 3519 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 3520 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 3521 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 3522 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 3523 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 3524 //VPMPCC_GAMUT_REMAP_COEF_FORMAT 3525 #define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 3526 #define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L 3527 //VPMPCC_GAMUT_REMAP_MODE 3528 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE__SHIFT 0x0 3529 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 3530 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_MASK 0x00000001L 3531 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000080L 3532 //VPMPC_GAMUT_REMAP_C11_C12_A 3533 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 3534 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 3535 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL 3536 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L 3537 //VPMPC_GAMUT_REMAP_C13_C14_A 3538 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 3539 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 3540 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL 3541 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L 3542 //VPMPC_GAMUT_REMAP_C21_C22_A 3543 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 3544 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 3545 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL 3546 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L 3547 //VPMPC_GAMUT_REMAP_C23_C24_A 3548 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 3549 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 3550 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL 3551 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L 3552 //VPMPC_GAMUT_REMAP_C31_C32_A 3553 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 3554 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 3555 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL 3556 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L 3557 //VPMPC_GAMUT_REMAP_C33_C34_A 3558 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 3559 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 3560 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL 3561 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L 3562 //VPMPCC_OGAM_TEST_DEBUG_INDEX 3563 #define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_INDEX__SHIFT 0x0 3564 #define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 3565 #define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_INDEX_MASK 0x000000FFL 3566 #define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3567 //VPMPCC_OGAM_TEST_DEBUG_DATA 3568 #define VPMPCC_OGAM_TEST_DEBUG_DATA__VPMPCC_OGAM_TEST_DEBUG_DATA__SHIFT 0x0 3569 #define VPMPCC_OGAM_TEST_DEBUG_DATA__VPMPCC_OGAM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 3570 3571 3572 // addressBlock: vpe_vpep_vpmpc_vpmpcc_mcm0_dispdec 3573 //VPMPCC_MCM_SHAPER_CONTROL 3574 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 3575 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 3576 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_SELECT_CURRENT__SHIFT 0x4 3577 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L 3578 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL 3579 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_SELECT_CURRENT_MASK 0x00000010L 3580 //VPMPCC_MCM_SHAPER_OFFSET_R 3581 #define VPMPCC_MCM_SHAPER_OFFSET_R__VPMPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 3582 #define VPMPCC_MCM_SHAPER_OFFSET_R__VPMPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL 3583 //VPMPCC_MCM_SHAPER_OFFSET_G 3584 #define VPMPCC_MCM_SHAPER_OFFSET_G__VPMPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 3585 #define VPMPCC_MCM_SHAPER_OFFSET_G__VPMPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL 3586 //VPMPCC_MCM_SHAPER_OFFSET_B 3587 #define VPMPCC_MCM_SHAPER_OFFSET_B__VPMPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 3588 #define VPMPCC_MCM_SHAPER_OFFSET_B__VPMPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL 3589 //VPMPCC_MCM_SHAPER_SCALE_R 3590 #define VPMPCC_MCM_SHAPER_SCALE_R__VPMPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 3591 #define VPMPCC_MCM_SHAPER_SCALE_R__VPMPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL 3592 //VPMPCC_MCM_SHAPER_SCALE_G_B 3593 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 3594 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 3595 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL 3596 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L 3597 //VPMPCC_MCM_SHAPER_LUT_INDEX 3598 #define VPMPCC_MCM_SHAPER_LUT_INDEX__VPMPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 3599 #define VPMPCC_MCM_SHAPER_LUT_INDEX__VPMPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL 3600 //VPMPCC_MCM_SHAPER_LUT_DATA 3601 #define VPMPCC_MCM_SHAPER_LUT_DATA__VPMPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 3602 #define VPMPCC_MCM_SHAPER_LUT_DATA__VPMPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL 3603 //VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 3604 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 3605 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 3606 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L 3607 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L 3608 //VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B 3609 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 3610 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 3611 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 3612 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 3613 //VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G 3614 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 3615 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 3616 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 3617 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 3618 //VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R 3619 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 3620 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 3621 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 3622 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 3623 //VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B 3624 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 3625 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 3626 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 3627 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L 3628 //VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G 3629 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 3630 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 3631 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 3632 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L 3633 //VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R 3634 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 3635 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 3636 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 3637 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L 3638 //VPMPCC_MCM_SHAPER_RAMA_REGION_0_1 3639 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 3640 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 3641 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 3642 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 3643 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 3644 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 3645 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 3646 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 3647 //VPMPCC_MCM_SHAPER_RAMA_REGION_2_3 3648 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 3649 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 3650 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 3651 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 3652 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 3653 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 3654 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 3655 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 3656 //VPMPCC_MCM_SHAPER_RAMA_REGION_4_5 3657 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 3658 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 3659 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 3660 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 3661 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 3662 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 3663 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 3664 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 3665 //VPMPCC_MCM_SHAPER_RAMA_REGION_6_7 3666 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 3667 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 3668 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 3669 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 3670 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 3671 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 3672 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 3673 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 3674 //VPMPCC_MCM_SHAPER_RAMA_REGION_8_9 3675 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 3676 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 3677 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 3678 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 3679 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 3680 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 3681 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 3682 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 3683 //VPMPCC_MCM_SHAPER_RAMA_REGION_10_11 3684 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 3685 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 3686 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 3687 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 3688 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 3689 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 3690 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 3691 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 3692 //VPMPCC_MCM_SHAPER_RAMA_REGION_12_13 3693 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 3694 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 3695 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 3696 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 3697 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 3698 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 3699 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 3700 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 3701 //VPMPCC_MCM_SHAPER_RAMA_REGION_14_15 3702 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 3703 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 3704 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 3705 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 3706 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 3707 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 3708 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 3709 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 3710 //VPMPCC_MCM_SHAPER_RAMA_REGION_16_17 3711 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 3712 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 3713 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 3714 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 3715 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 3716 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 3717 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 3718 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 3719 //VPMPCC_MCM_SHAPER_RAMA_REGION_18_19 3720 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 3721 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 3722 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 3723 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 3724 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 3725 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 3726 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 3727 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 3728 //VPMPCC_MCM_SHAPER_RAMA_REGION_20_21 3729 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 3730 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 3731 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 3732 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 3733 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 3734 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 3735 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 3736 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 3737 //VPMPCC_MCM_SHAPER_RAMA_REGION_22_23 3738 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 3739 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 3740 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 3741 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 3742 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 3743 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 3744 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 3745 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 3746 //VPMPCC_MCM_SHAPER_RAMA_REGION_24_25 3747 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 3748 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 3749 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 3750 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 3751 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 3752 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 3753 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 3754 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 3755 //VPMPCC_MCM_SHAPER_RAMA_REGION_26_27 3756 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 3757 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 3758 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 3759 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 3760 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 3761 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 3762 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 3763 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 3764 //VPMPCC_MCM_SHAPER_RAMA_REGION_28_29 3765 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 3766 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 3767 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 3768 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 3769 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 3770 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 3771 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 3772 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 3773 //VPMPCC_MCM_SHAPER_RAMA_REGION_30_31 3774 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 3775 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 3776 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 3777 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 3778 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 3779 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 3780 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 3781 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 3782 //VPMPCC_MCM_SHAPER_RAMA_REGION_32_33 3783 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 3784 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 3785 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 3786 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 3787 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 3788 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 3789 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 3790 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 3791 //VPMPCC_MCM_3DLUT_MODE 3792 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE__SHIFT 0x0 3793 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SIZE__SHIFT 0x4 3794 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 3795 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SELECT_CURRENT__SHIFT 0xa 3796 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_MASK 0x00000003L 3797 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SIZE_MASK 0x00000010L 3798 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L 3799 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SELECT_CURRENT_MASK 0x00000400L 3800 //VPMPCC_MCM_3DLUT_INDEX 3801 #define VPMPCC_MCM_3DLUT_INDEX__VPMPCC_MCM_3DLUT_INDEX__SHIFT 0x0 3802 #define VPMPCC_MCM_3DLUT_INDEX__VPMPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL 3803 //VPMPCC_MCM_3DLUT_DATA 3804 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA0__SHIFT 0x0 3805 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA1__SHIFT 0x10 3806 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL 3807 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L 3808 //VPMPCC_MCM_3DLUT_DATA_30BIT 3809 #define VPMPCC_MCM_3DLUT_DATA_30BIT__VPMPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 3810 #define VPMPCC_MCM_3DLUT_DATA_30BIT__VPMPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL 3811 //VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL 3812 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 3813 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 3814 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 3815 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 3816 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL 3817 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L 3818 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L 3819 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L 3820 //VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR 3821 #define VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 3822 #define VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL 3823 //VPMPCC_MCM_3DLUT_OUT_OFFSET_R 3824 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 3825 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 3826 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL 3827 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L 3828 //VPMPCC_MCM_3DLUT_OUT_OFFSET_G 3829 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 3830 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 3831 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL 3832 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L 3833 //VPMPCC_MCM_3DLUT_OUT_OFFSET_B 3834 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 3835 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 3836 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL 3837 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L 3838 //VPMPCC_MCM_1DLUT_CONTROL 3839 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE__SHIFT 0x0 3840 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 3841 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 3842 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 3843 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_MASK 0x00000003L 3844 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L 3845 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L 3846 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L 3847 //VPMPCC_MCM_1DLUT_LUT_INDEX 3848 #define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 3849 #define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL 3850 //VPMPCC_MCM_1DLUT_LUT_DATA 3851 #define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 3852 #define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL 3853 //VPMPCC_MCM_1DLUT_LUT_CONTROL 3854 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 3855 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 3856 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 3857 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 3858 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 3859 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L 3860 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L 3861 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L 3862 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L 3863 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L 3864 //VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 3865 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 3866 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 3867 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 3868 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 3869 //VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 3870 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 3871 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 3872 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 3873 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 3874 //VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 3875 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 3876 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 3877 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 3878 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 3879 //VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 3880 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 3881 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL 3882 //VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 3883 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 3884 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL 3885 //VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 3886 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 3887 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL 3888 //VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 3889 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 3890 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL 3891 //VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 3892 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 3893 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL 3894 //VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 3895 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 3896 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL 3897 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 3898 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 3899 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL 3900 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 3901 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 3902 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 3903 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 3904 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L 3905 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 3906 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 3907 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL 3908 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 3909 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 3910 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 3911 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 3912 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L 3913 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 3914 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 3915 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL 3916 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 3917 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 3918 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 3919 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 3920 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L 3921 //VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 3922 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 3923 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL 3924 //VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 3925 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 3926 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL 3927 //VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 3928 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 3929 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL 3930 //VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 3931 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 3932 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 3933 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 3934 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 3935 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 3936 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 3937 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 3938 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 3939 //VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 3940 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 3941 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 3942 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 3943 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 3944 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 3945 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 3946 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 3947 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 3948 //VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 3949 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 3950 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 3951 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 3952 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 3953 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 3954 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 3955 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 3956 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 3957 //VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 3958 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 3959 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 3960 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 3961 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 3962 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 3963 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 3964 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 3965 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 3966 //VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 3967 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 3968 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 3969 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 3970 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 3971 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 3972 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 3973 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 3974 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 3975 //VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 3976 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 3977 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 3978 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 3979 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 3980 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 3981 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 3982 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 3983 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 3984 //VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 3985 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 3986 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 3987 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 3988 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 3989 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 3990 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 3991 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 3992 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 3993 //VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 3994 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 3995 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 3996 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 3997 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 3998 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 3999 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 4000 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 4001 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 4002 //VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 4003 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 4004 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 4005 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 4006 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 4007 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 4008 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 4009 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 4010 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 4011 //VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 4012 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 4013 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 4014 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 4015 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 4016 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 4017 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 4018 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 4019 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 4020 //VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 4021 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 4022 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 4023 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 4024 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 4025 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 4026 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 4027 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 4028 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 4029 //VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 4030 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 4031 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 4032 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 4033 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 4034 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 4035 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 4036 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 4037 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 4038 //VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 4039 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 4040 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 4041 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 4042 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 4043 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 4044 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 4045 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 4046 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 4047 //VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 4048 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 4049 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 4050 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 4051 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 4052 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 4053 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 4054 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 4055 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 4056 //VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 4057 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 4058 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 4059 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 4060 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 4061 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 4062 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 4063 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 4064 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 4065 //VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 4066 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 4067 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 4068 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 4069 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 4070 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 4071 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 4072 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 4073 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 4074 //VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 4075 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 4076 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 4077 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 4078 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 4079 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 4080 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 4081 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 4082 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 4083 //VPMPCC_MCM_MEM_PWR_CTRL 4084 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 4085 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 4086 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 4087 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 4088 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa 4089 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc 4090 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 4091 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 4092 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 4093 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 4094 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a 4095 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c 4096 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L 4097 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L 4098 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L 4099 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L 4100 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L 4101 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L 4102 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L 4103 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L 4104 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L 4105 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L 4106 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L 4107 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L 4108 //VPMPCC_MCM_TEST_DEBUG_INDEX 4109 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX__SHIFT 0x0 4110 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 4111 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX_MASK 0x000000FFL 4112 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4113 //VPMPCC_MCM_TEST_DEBUG_DATA 4114 #define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA__SHIFT 0x0 4115 #define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 4116 4117 4118 // addressBlock: vpe_vpep_vpmpc_vpmpc_ocsc_dispdec 4119 //VPMPC_OUT0_MUX 4120 #define VPMPC_OUT0_MUX__VPMPC_OUT_MUX__SHIFT 0x0 4121 #define VPMPC_OUT0_MUX__VPMPC_OUT_MUX_MASK 0x0000000FL 4122 //VPMPC_OUT0_FLOAT_CONTROL 4123 #define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN__SHIFT 0x0 4124 #define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK 0x00000001L 4125 //VPMPC_OUT0_DENORM_CONTROL 4126 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 4127 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc 4128 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE__SHIFT 0x18 4129 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL 4130 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L 4131 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000L 4132 //VPMPC_OUT0_DENORM_CLAMP_G_Y 4133 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 4134 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc 4135 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL 4136 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L 4137 //VPMPC_OUT0_DENORM_CLAMP_B_CB 4138 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 4139 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc 4140 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL 4141 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L 4142 //VPMPC_OUT_CSC_COEF_FORMAT 4143 #define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT__SHIFT 0x0 4144 #define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT_MASK 0x00000001L 4145 //VPMPC_OUT0_CSC_MODE 4146 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE__SHIFT 0x0 4147 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT__SHIFT 0x7 4148 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_MASK 0x00000001L 4149 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK 0x00000080L 4150 //VPMPC_OUT0_CSC_C11_C12_A 4151 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A__SHIFT 0x0 4152 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A__SHIFT 0x10 4153 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK 0x0000FFFFL 4154 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK 0xFFFF0000L 4155 //VPMPC_OUT0_CSC_C13_C14_A 4156 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A__SHIFT 0x0 4157 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A__SHIFT 0x10 4158 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK 0x0000FFFFL 4159 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK 0xFFFF0000L 4160 //VPMPC_OUT0_CSC_C21_C22_A 4161 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A__SHIFT 0x0 4162 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A__SHIFT 0x10 4163 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK 0x0000FFFFL 4164 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK 0xFFFF0000L 4165 //VPMPC_OUT0_CSC_C23_C24_A 4166 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A__SHIFT 0x0 4167 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A__SHIFT 0x10 4168 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK 0x0000FFFFL 4169 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK 0xFFFF0000L 4170 //VPMPC_OUT0_CSC_C31_C32_A 4171 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A__SHIFT 0x0 4172 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A__SHIFT 0x10 4173 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK 0x0000FFFFL 4174 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK 0xFFFF0000L 4175 //VPMPC_OUT0_CSC_C33_C34_A 4176 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A__SHIFT 0x0 4177 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A__SHIFT 0x10 4178 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK 0x0000FFFFL 4179 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK 0xFFFF0000L 4180 //VPMPC_OCSC_TEST_DEBUG_INDEX 4181 #define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_INDEX__SHIFT 0x0 4182 #define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 4183 #define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_INDEX_MASK 0x000000FFL 4184 #define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4185 //VPMPC_OCSC_TEST_DEBUG_DATA 4186 #define VPMPC_OCSC_TEST_DEBUG_DATA__VPMPC_OCSC_TEST_DEBUG_DATA__SHIFT 0x0 4187 #define VPMPC_OCSC_TEST_DEBUG_DATA__VPMPC_OCSC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 4188 4189 4190 // addressBlock: vpe_vpep_vpopp_vpfmt0_dispdec 4191 //VPFMT_CLAMP_COMPONENT_R 4192 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R__SHIFT 0x0 4193 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R__SHIFT 0x10 4194 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R_MASK 0x0000FFFFL 4195 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R_MASK 0xFFFF0000L 4196 //VPFMT_CLAMP_COMPONENT_G 4197 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G__SHIFT 0x0 4198 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G__SHIFT 0x10 4199 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G_MASK 0x0000FFFFL 4200 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G_MASK 0xFFFF0000L 4201 //VPFMT_CLAMP_COMPONENT_B 4202 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B__SHIFT 0x0 4203 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B__SHIFT 0x10 4204 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B_MASK 0x0000FFFFL 4205 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B_MASK 0xFFFF0000L 4206 //VPFMT_DYNAMIC_EXP_CNTL 4207 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN__SHIFT 0x0 4208 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE__SHIFT 0x4 4209 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN_MASK 0x00000001L 4210 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE_MASK 0x00000010L 4211 //VPFMT_CONTROL 4212 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 4213 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc 4214 #define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 4215 #define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 4216 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L 4217 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L 4218 #define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L 4219 #define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L 4220 //VPFMT_BIT_DEPTH_CONTROL 4221 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN__SHIFT 0x0 4222 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE__SHIFT 0x1 4223 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH__SHIFT 0x4 4224 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN__SHIFT 0x8 4225 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE__SHIFT 0x9 4226 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb 4227 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE__SHIFT 0xd 4228 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE__SHIFT 0xe 4229 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf 4230 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN_MASK 0x00000001L 4231 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE_MASK 0x00000002L 4232 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH_MASK 0x00000030L 4233 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN_MASK 0x00000100L 4234 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE_MASK 0x00000600L 4235 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L 4236 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L 4237 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE_MASK 0x00004000L 4238 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L 4239 //VPFMT_DITHER_RAND_R_SEED 4240 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED__SHIFT 0x0 4241 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR__SHIFT 0x10 4242 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED_MASK 0x000000FFL 4243 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR_MASK 0xFFFF0000L 4244 //VPFMT_DITHER_RAND_G_SEED 4245 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED__SHIFT 0x0 4246 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y__SHIFT 0x10 4247 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED_MASK 0x000000FFL 4248 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y_MASK 0xFFFF0000L 4249 //VPFMT_DITHER_RAND_B_SEED 4250 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED__SHIFT 0x0 4251 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB__SHIFT 0x10 4252 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED_MASK 0x000000FFL 4253 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB_MASK 0xFFFF0000L 4254 //VPFMT_CLAMP_CNTL 4255 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN__SHIFT 0x0 4256 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 4257 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN_MASK 0x00000001L 4258 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L 4259 //VPFMT_DEBUG_CNTL 4260 #define VPFMT_DEBUG_CNTL__VPFMT_DEBUG_COLOR_SELECT__SHIFT 0x0 4261 #define VPFMT_DEBUG_CNTL__VPFMT_DEBUG_COLOR_SELECT_MASK 0x00000003L 4262 //VPFMT_TEST_DEBUG_INDEX 4263 #define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_INDEX__SHIFT 0x0 4264 #define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 4265 #define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_INDEX_MASK 0x000000FFL 4266 #define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4267 //VPFMT_TEST_DEBUG_DATA 4268 #define VPFMT_TEST_DEBUG_DATA__VPFMT_TEST_DEBUG_DATA__SHIFT 0x0 4269 #define VPFMT_TEST_DEBUG_DATA__VPFMT_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 4270 4271 4272 // addressBlock: vpe_vpep_vpopp_vpopp_pipe0_dispdec 4273 //VPOPP_PIPE_CONTROL 4274 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON__SHIFT 0x1 4275 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 4276 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA__SHIFT 0x10 4277 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON_MASK 0x00000002L 4278 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L 4279 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_MASK 0xFFFF0000L 4280 //VPOPP_PIPE_SPARE_DEBUG 4281 #define VPOPP_PIPE_SPARE_DEBUG__VPOPP_PIPE_SPARE_DEBUG__SHIFT 0x0 4282 #define VPOPP_PIPE_SPARE_DEBUG__VPOPP_PIPE_SPARE_DEBUG_MASK 0xFFFFFFFFL 4283 //VPOPP_PIPE_TEST_DEBUG_INDEX 4284 #define VPOPP_PIPE_TEST_DEBUG_INDEX__VPOPP_PIPE_TEST_DEBUG_INDEX__SHIFT 0x0 4285 #define VPOPP_PIPE_TEST_DEBUG_INDEX__VPOPP_PIPE_TEST_DEBUG_INDEX_MASK 0x000000FFL 4286 //VPOPP_PIPE_TEST_DEBUG_DATA 4287 #define VPOPP_PIPE_TEST_DEBUG_DATA__VPOPP_PIPE_TEST_DEBUG_DATA__SHIFT 0x0 4288 #define VPOPP_PIPE_TEST_DEBUG_DATA__VPOPP_PIPE_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 4289 4290 4291 // addressBlock: vpe_vpep_vpopp_vpopp_pipe_crc0_dispdec 4292 //VPOPP_PIPE_CRC_CONTROL 4293 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_EN__SHIFT 0x0 4294 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_CONT_EN__SHIFT 0x4 4295 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 4296 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c 4297 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_EN_MASK 0x00000001L 4298 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_CONT_EN_MASK 0x00000010L 4299 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L 4300 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L 4301 //VPOPP_PIPE_CRC_MASK 4302 #define VPOPP_PIPE_CRC_MASK__VPOPP_PIPE_CRC_MASK__SHIFT 0x0 4303 #define VPOPP_PIPE_CRC_MASK__VPOPP_PIPE_CRC_MASK_MASK 0x0000FFFFL 4304 //VPOPP_PIPE_CRC_RESULT0 4305 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_A__SHIFT 0x0 4306 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_R__SHIFT 0x10 4307 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL 4308 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L 4309 //VPOPP_PIPE_CRC_RESULT1 4310 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_G__SHIFT 0x0 4311 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_B__SHIFT 0x10 4312 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL 4313 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L 4314 //VPOPP_PIPE_CRC_RESULT2 4315 #define VPOPP_PIPE_CRC_RESULT2__VPOPP_PIPE_CRC_RESULT_C__SHIFT 0x0 4316 #define VPOPP_PIPE_CRC_RESULT2__VPOPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL 4317 4318 4319 // addressBlock: vpe_vpep_vpopp_vpopp_top_dispdec 4320 //VPOPP_TOP_CLK_CONTROL 4321 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS__SHIFT 0x0 4322 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS__SHIFT 0x1 4323 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS_MASK 0x00000001L 4324 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS_MASK 0x00000002L 4325 //VPOPP_DEBUG_CONTROL 4326 #define VPOPP_DEBUG_CONTROL__VPOPP_DBG_EN__SHIFT 0x0 4327 #define VPOPP_DEBUG_CONTROL__VPOPP_VPFMT_DEBUG_BUS_SELECT__SHIFT 0x4 4328 #define VPOPP_DEBUG_CONTROL__VPOPP_VPOPP_PIPE_DEBUG_BUS_SELECT__SHIFT 0x10 4329 #define VPOPP_DEBUG_CONTROL__VPOPP_DBG_EN_MASK 0x00000001L 4330 #define VPOPP_DEBUG_CONTROL__VPOPP_VPFMT_DEBUG_BUS_SELECT_MASK 0x000000F0L 4331 #define VPOPP_DEBUG_CONTROL__VPOPP_VPOPP_PIPE_DEBUG_BUS_SELECT_MASK 0x00070000L 4332 //VPOPP_TOP_SPARE_DEBUG 4333 #define VPOPP_TOP_SPARE_DEBUG__VPOPP_TOP_SPARE_DEBUG__SHIFT 0x0 4334 #define VPOPP_TOP_SPARE_DEBUG__VPOPP_TOP_SPARE_DEBUG_MASK 0xFFFFFFFFL 4335 //VPOPP_TOP_TEST_DEBUG_INDEX 4336 #define VPOPP_TOP_TEST_DEBUG_INDEX__VPOPP_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 4337 #define VPOPP_TOP_TEST_DEBUG_INDEX__VPOPP_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL 4338 //VPOPP_TOP_TEST_DEBUG_DATA 4339 #define VPOPP_TOP_TEST_DEBUG_DATA__VPOPP_TOP_TEST_DEBUG_DATA__SHIFT 0x0 4340 #define VPOPP_TOP_TEST_DEBUG_DATA__VPOPP_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 4341 4342 4343 // addressBlock: vpe_vpep_vpcdc_cdc_dispdec 4344 //VPEP_MGCG_CNTL 4345 #define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS__SHIFT 0x0 4346 #define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS__SHIFT 0xc 4347 #define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS__SHIFT 0x12 4348 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS__SHIFT 0x14 4349 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS__SHIFT 0x15 4350 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS__SHIFT 0x16 4351 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS__SHIFT 0x17 4352 #define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS_MASK 0x00000007L 4353 #define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS_MASK 0x00003000L 4354 #define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS_MASK 0x000C0000L 4355 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS_MASK 0x00100000L 4356 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS_MASK 0x00200000L 4357 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS_MASK 0x00400000L 4358 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS_MASK 0x00800000L 4359 //VPCDC_SOFT_RESET 4360 #define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET__SHIFT 0x0 4361 #define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET__SHIFT 0x1 4362 #define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET_MASK 0x00000001L 4363 #define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET_MASK 0x00000002L 4364 //VPCDC_FE0_SURFACE_CONFIG 4365 #define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0__SHIFT 0x0 4366 #define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0__SHIFT 0x8 4367 #define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0__SHIFT 0xa 4368 #define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0__SHIFT 0xb 4369 #define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0_MASK 0x0000007FL 4370 #define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0_MASK 0x00000300L 4371 #define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0_MASK 0x00000400L 4372 #define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0_MASK 0x00000800L 4373 //VPCDC_FE0_CROSSBAR_CONFIG 4374 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0__SHIFT 0x0 4375 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0__SHIFT 0x2 4376 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0__SHIFT 0x4 4377 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0__SHIFT 0x6 4378 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0_MASK 0x00000003L 4379 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0_MASK 0x0000000CL 4380 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0_MASK 0x00000030L 4381 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0_MASK 0x000000C0L 4382 //VPCDC_FE0_VIEWPORT_START_CONFIG 4383 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0__SHIFT 0x0 4384 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0__SHIFT 0x10 4385 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0_MASK 0x00003FFFL 4386 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0_MASK 0x3FFF0000L 4387 //VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG 4388 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0__SHIFT 0x0 4389 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0__SHIFT 0x10 4390 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0_MASK 0x00003FFFL 4391 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0_MASK 0x3FFF0000L 4392 //VPCDC_FE0_VIEWPORT_START_C_CONFIG 4393 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0__SHIFT 0x0 4394 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0__SHIFT 0x10 4395 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0_MASK 0x00003FFFL 4396 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0_MASK 0x3FFF0000L 4397 //VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG 4398 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0__SHIFT 0x0 4399 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0__SHIFT 0x10 4400 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0_MASK 0x00003FFFL 4401 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0_MASK 0x3FFF0000L 4402 //VPCDC_BE0_P2B_CONFIG 4403 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0__SHIFT 0x0 4404 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1__SHIFT 0x2 4405 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2__SHIFT 0x4 4406 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3__SHIFT 0x6 4407 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL__SHIFT 0x8 4408 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0_MASK 0x00000003L 4409 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1_MASK 0x0000000CL 4410 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2_MASK 0x00000030L 4411 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3_MASK 0x000000C0L 4412 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL_MASK 0x00000300L 4413 //VPCDC_BE0_GLOBAL_SYNC_CONFIG 4414 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET__SHIFT 0x0 4415 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH__SHIFT 0xa 4416 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET__SHIFT 0x14 4417 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET_MASK 0x000003FFL 4418 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH_MASK 0x000FFC00L 4419 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET_MASK 0x3FF00000L 4420 //VPCDC_GLOBAL_SYNC_TRIGGER 4421 #define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG__SHIFT 0x0 4422 #define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG_MASK 0x00000003L 4423 //VPCDC_VREADY_STATUS 4424 #define VPCDC_VREADY_STATUS__VPFE_VR_STATUS__SHIFT 0x0 4425 #define VPCDC_VREADY_STATUS__VPFE_VR_STATUS_MASK 0x00000003L 4426 //VPEP_MEM_GLOBAL_PWR_REQ_CNTL 4427 #define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 4428 #define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L 4429 //VPFE_MEM_PWR_CNTL 4430 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE__SHIFT 0x0 4431 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE__SHIFT 0x2 4432 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE__SHIFT 0x4 4433 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS__SHIFT 0x6 4434 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE_MASK 0x00000003L 4435 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE_MASK 0x0000000CL 4436 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE_MASK 0x00000030L 4437 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS_MASK 0x00000040L 4438 //VPBE_MEM_PWR_CNTL 4439 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE__SHIFT 0x0 4440 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE__SHIFT 0x2 4441 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE__SHIFT 0x4 4442 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS__SHIFT 0x6 4443 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE_MASK 0x00000003L 4444 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE_MASK 0x0000000CL 4445 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE_MASK 0x00000030L 4446 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS_MASK 0x00000040L 4447 //VPEP_RBBMIF_TIMEOUT 4448 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 4449 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD__SHIFT 0x14 4450 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL 4451 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD_MASK 0xFFF00000L 4452 //VPEP_RBBMIF_STATUS 4453 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 4454 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c 4455 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d 4456 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e 4457 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f 4458 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000000FL 4459 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L 4460 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L 4461 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L 4462 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L 4463 //VPEP_RBBMIF_TIMEOUT_DIS 4464 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 4465 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 4466 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 4467 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 4468 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L 4469 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L 4470 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L 4471 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L 4472 //VPCDC_DEBUG_CTRL0 4473 #define VPCDC_DEBUG_CTRL0__VPCDC_DBG_EN__SHIFT 0x0 4474 #define VPCDC_DEBUG_CTRL0__VPCDC_DBGMUX_OUT_0_SEL_SOCCLK__SHIFT 0x14 4475 #define VPCDC_DEBUG_CTRL0__VPCDC_DBG_EN_MASK 0x00000001L 4476 #define VPCDC_DEBUG_CTRL0__VPCDC_DBGMUX_OUT_0_SEL_SOCCLK_MASK 0x00700000L 4477 //VPCDC_DEBUG_CTRL1 4478 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_0_SEL_VPECLK__SHIFT 0x0 4479 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_1_SEL_VPECLK__SHIFT 0x8 4480 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_2_SEL_VPECLK__SHIFT 0x10 4481 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_3_SEL_VPECLK__SHIFT 0x18 4482 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_0_SEL_VPECLK_MASK 0x0000001FL 4483 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_1_SEL_VPECLK_MASK 0x00001F00L 4484 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_2_SEL_VPECLK_MASK 0x001F0000L 4485 #define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_3_SEL_VPECLK_MASK 0x1F000000L 4486 //VPCDC_TEST_DEBUG_INDEX 4487 #define VPCDC_TEST_DEBUG_INDEX__VPCDC_TEST_DEBUG_INDEX__SHIFT 0x0 4488 #define VPCDC_TEST_DEBUG_INDEX__VPCDC_TEST_DEBUG_INDEX_MASK 0x000000FFL 4489 //VPCDC_TEST_DEBUG_DATA 4490 #define VPCDC_TEST_DEBUG_DATA__VPCDC_TEST_DEBUG_DATA__SHIFT 0x0 4491 #define VPCDC_TEST_DEBUG_DATA__VPCDC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 4492 4493 4494 // addressBlock: vpe_vpep_vpcdc_vpcdc_dcperfmon_dc_perfmon_dispdec 4495 //PERFCOUNTER_CNTL 4496 #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 4497 #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 4498 #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc 4499 #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf 4500 #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 4501 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 4502 #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 4503 #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 4504 #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 4505 #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a 4506 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d 4507 #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL 4508 #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L 4509 #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L 4510 #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L 4511 #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L 4512 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L 4513 #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L 4514 #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L 4515 #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L 4516 #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L 4517 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L 4518 //PERFCOUNTER_CNTL2 4519 #define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 4520 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 4521 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 4522 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 4523 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d 4524 #define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L 4525 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L 4526 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L 4527 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L 4528 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L 4529 //PERFCOUNTER_STATE 4530 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 4531 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 4532 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 4533 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 4534 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 4535 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa 4536 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc 4537 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe 4538 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 4539 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 4540 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 4541 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 4542 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 4543 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a 4544 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c 4545 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e 4546 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L 4547 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L 4548 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L 4549 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L 4550 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L 4551 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L 4552 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L 4553 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L 4554 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L 4555 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L 4556 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L 4557 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L 4558 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L 4559 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L 4560 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L 4561 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L 4562 //PERFMON_CNTL 4563 #define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 4564 #define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 4565 #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c 4566 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d 4567 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e 4568 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f 4569 #define PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L 4570 #define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L 4571 #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L 4572 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L 4573 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L 4574 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L 4575 //PERFMON_CNTL2 4576 #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 4577 #define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 4578 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 4579 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa 4580 #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L 4581 #define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L 4582 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL 4583 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L 4584 //PERFMON_CVALUE_INT_MISC 4585 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 4586 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 4587 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 4588 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 4589 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 4590 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 4591 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 4592 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 4593 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 4594 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 4595 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa 4596 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb 4597 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc 4598 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd 4599 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe 4600 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf 4601 #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 4602 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L 4603 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L 4604 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L 4605 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L 4606 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L 4607 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L 4608 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L 4609 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L 4610 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L 4611 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L 4612 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L 4613 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L 4614 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L 4615 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L 4616 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L 4617 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L 4618 #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L 4619 //PERFMON_CVALUE_LOW 4620 #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 4621 #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL 4622 //PERFMON_HI 4623 #define PERFMON_HI__PERFMON_HI__SHIFT 0x0 4624 #define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d 4625 #define PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL 4626 #define PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L 4627 //PERFMON_LOW 4628 #define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 4629 #define PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL 4630 //PERFMON_TEST_DEBUG_INDEX 4631 #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 4632 #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 4633 #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0x000000FFL 4634 #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4635 //PERFMON_TEST_DEBUG_DATA 4636 #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 4637 #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 4638 4639 4640 // addressBlock: dc_perfmon_dc_perfmondebugind 4641 //PERFMON_DEBUG_ID 4642 #define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID__SHIFT 0x0 4643 #define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID_MASK 0xFFFFFFFFL 4644 //PERFMON_DEBUG01 4645 #define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW__SHIFT 0x0 4646 #define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4647 //PERFMON_DEBUG02 4648 #define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI__SHIFT 0x0 4649 #define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT__SHIFT 0x10 4650 #define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI_MASK 0x0000FFFFL 4651 #define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT_MASK 0x001F0000L 4652 //PERFMON_DEBUG03 4653 #define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW__SHIFT 0x0 4654 #define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4655 //PERFMON_DEBUG04 4656 #define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI__SHIFT 0x0 4657 #define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT__SHIFT 0x10 4658 #define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI_MASK 0x0000FFFFL 4659 #define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT_MASK 0x001F0000L 4660 //PERFMON_DEBUG05 4661 #define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW__SHIFT 0x0 4662 #define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4663 //PERFMON_DEBUG06 4664 #define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI__SHIFT 0x0 4665 #define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT__SHIFT 0x10 4666 #define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI_MASK 0x0000FFFFL 4667 #define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT_MASK 0x001F0000L 4668 //PERFMON_DEBUG07 4669 #define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW__SHIFT 0x0 4670 #define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4671 //PERFMON_DEBUG08 4672 #define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI__SHIFT 0x0 4673 #define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT__SHIFT 0x10 4674 #define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI_MASK 0x0000FFFFL 4675 #define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT_MASK 0x001F0000L 4676 //PERFMON_DEBUG09 4677 #define PERFMON_DEBUG09__PERFMON_EN_EVENT_START__SHIFT 0x0 4678 #define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP__SHIFT 0x1 4679 #define PERFMON_DEBUG09__PERFMON_EN_EVENT_START_MASK 0x00000001L 4680 #define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP_MASK 0x00000002L 4681 //PERFMON_DEBUG0A 4682 #define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW__SHIFT 0x0 4683 #define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4684 //PERFMON_DEBUG0B 4685 #define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI__SHIFT 0x0 4686 #define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT__SHIFT 0x10 4687 #define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI_MASK 0x0000FFFFL 4688 #define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT_MASK 0x001F0000L 4689 //PERFMON_DEBUG0C 4690 #define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW__SHIFT 0x0 4691 #define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4692 //PERFMON_DEBUG0D 4693 #define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI__SHIFT 0x0 4694 #define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT__SHIFT 0x10 4695 #define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI_MASK 0x0000FFFFL 4696 #define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT_MASK 0x001F0000L 4697 //PERFMON_DEBUG0E 4698 #define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW__SHIFT 0x0 4699 #define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4700 //PERFMON_DEBUG0F 4701 #define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI__SHIFT 0x0 4702 #define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT__SHIFT 0x10 4703 #define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI_MASK 0x0000FFFFL 4704 #define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT_MASK 0x001F0000L 4705 //PERFMON_DEBUG10 4706 #define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW__SHIFT 0x0 4707 #define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL 4708 //PERFMON_DEBUG11 4709 #define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI__SHIFT 0x0 4710 #define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT__SHIFT 0x10 4711 #define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI_MASK 0x0000FFFFL 4712 #define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT_MASK 0x001F0000L 4713 //PERFMON_DEBUG12 4714 #define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF__SHIFT 0x0 4715 #define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF__SHIFT 0x1 4716 #define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF__SHIFT 0x2 4717 #define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF__SHIFT 0x3 4718 #define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF__SHIFT 0x4 4719 #define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF__SHIFT 0x5 4720 #define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF__SHIFT 0x6 4721 #define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF__SHIFT 0x7 4722 #define PERFMON_DEBUG12__PERFCOUNTER_OFF__SHIFT 0x8 4723 #define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF_MASK 0x00000001L 4724 #define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF_MASK 0x00000002L 4725 #define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF_MASK 0x00000004L 4726 #define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF_MASK 0x00000008L 4727 #define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF_MASK 0x00000010L 4728 #define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF_MASK 0x00000020L 4729 #define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF_MASK 0x00000040L 4730 #define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF_MASK 0x00000080L 4731 #define PERFMON_DEBUG12__PERFCOUNTER_OFF_MASK 0x00000100L 4732 4733 4734 // addressBlock: vpfmt0_vpfmtdebugind 4735 //VPFMT_DEBUG_ID 4736 #define VPFMT_DEBUG_ID__VPFMT_DEBUG_ID__SHIFT 0x0 4737 #define VPFMT_DEBUG_ID__VPFMT_DEBUG_ID_MASK 0xFFFFFFFFL 4738 //VPFMT_DEBUG0 4739 #define VPFMT_DEBUG0__VPFMT_DEBUG0__SHIFT 0x0 4740 #define VPFMT_DEBUG0__VPFMT_DEBUG0_MASK 0xFFFFFFFFL 4741 //VPFMT_DEBUG1 4742 #define VPFMT_DEBUG1__VPFMT_DEBUG1__SHIFT 0x0 4743 #define VPFMT_DEBUG1__VPFMT_DEBUG1_MASK 0xFFFFFFFFL 4744 //VPFMT_DEBUG2 4745 #define VPFMT_DEBUG2__VPFMT_DEBUG2__SHIFT 0x0 4746 #define VPFMT_DEBUG2__VPFMT_DEBUG2_MASK 0xFFFFFFFFL 4747 //VPFMT_DEBUG3 4748 #define VPFMT_DEBUG3__VPFMT_DEBUG3__SHIFT 0x0 4749 #define VPFMT_DEBUG3__VPFMT_DEBUG3_MASK 0xFFFFFFFFL 4750 //VPFMT_DEBUG4 4751 #define VPFMT_DEBUG4__VPFMT_DEBUG4__SHIFT 0x0 4752 #define VPFMT_DEBUG4__VPFMT_DEBUG4_MASK 0xFFFFFFFFL 4753 //VPFMT_DEBUG5 4754 #define VPFMT_DEBUG5__VPFMT_DEBUG5__SHIFT 0x0 4755 #define VPFMT_DEBUG5__VPFMT_DEBUG5_MASK 0xFFFFFFFFL 4756 //VPFMT_DEBUG6 4757 #define VPFMT_DEBUG6__VPFMT_DEBUG6__SHIFT 0x0 4758 #define VPFMT_DEBUG6__VPFMT_DEBUG6_MASK 0xFFFFFFFFL 4759 //VPFMT_DEBUG7 4760 #define VPFMT_DEBUG7__VPFMT_DEBUG7__SHIFT 0x0 4761 #define VPFMT_DEBUG7__VPFMT_DEBUG7_MASK 0xFFFFFFFFL 4762 //VPFMT_DEBUG8 4763 #define VPFMT_DEBUG8__VPFMT_DEBUG8__SHIFT 0x0 4764 #define VPFMT_DEBUG8__VPFMT_DEBUG8_MASK 0xFFFFFFFFL 4765 //VPFMT_DEBUG9 4766 #define VPFMT_DEBUG9__VPFMT_DEBUG9__SHIFT 0x0 4767 #define VPFMT_DEBUG9__VPFMT_DEBUG9_MASK 0xFFFFFFFFL 4768 //VPFMT_DEBUG10 4769 #define VPFMT_DEBUG10__VPFMT_DEBUG10__SHIFT 0x0 4770 #define VPFMT_DEBUG10__VPFMT_DEBUG10_MASK 0xFFFFFFFFL 4771 //VPFMT_DEBUG11 4772 #define VPFMT_DEBUG11__VPFMT_DEBUG11__SHIFT 0x0 4773 #define VPFMT_DEBUG11__VPFMT_DEBUG11_MASK 0xFFFFFFFFL 4774 4775 4776 // addressBlock: vpopp_pipe0_vpopppipedebugind 4777 //VPOPP_PIPE_DEBUG_ID 4778 #define VPOPP_PIPE_DEBUG_ID__VPOPP_PIPE_DEBUG_ID__SHIFT 0x0 4779 #define VPOPP_PIPE_DEBUG_ID__VPOPP_PIPE_DEBUG_ID_MASK 0xFFFFFFFFL 4780 //VPOPP_PIPE_DEBUG_0 4781 #define VPOPP_PIPE_DEBUG_0__VPOPP_PIPE_DEBUG_0__SHIFT 0x0 4782 #define VPOPP_PIPE_DEBUG_0__VPOPP_PIPE_DEBUG_0_MASK 0xFFFFFFFFL 4783 //VPOPP_PIPE_DEBUG_1 4784 #define VPOPP_PIPE_DEBUG_1__VPOPP_PIPE_DEBUG_1__SHIFT 0x0 4785 #define VPOPP_PIPE_DEBUG_1__VPOPP_PIPE_DEBUG_1_MASK 0xFFFFFFFFL 4786 //VPOPP_PIPE_DEBUG_2 4787 #define VPOPP_PIPE_DEBUG_2__VPOPP_PIPE_DEBUG_2__SHIFT 0x0 4788 #define VPOPP_PIPE_DEBUG_2__VPOPP_PIPE_DEBUG_2_MASK 0xFFFFFFFFL 4789 4790 4791 // addressBlock: vpopp_top_vpopp_topdebugind 4792 //VPOPP_TOP_DEBUG_ID 4793 #define VPOPP_TOP_DEBUG_ID__VPOPP_TOP_DEBUG_ID__SHIFT 0x0 4794 #define VPOPP_TOP_DEBUG_ID__VPOPP_TOP_DEBUG_ID_MASK 0xFFFFFFFFL 4795 4796 #endif 4797