1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 #if !defined (__GFX10_GB_REG_H__) 10 #define __GFX10_GB_REG_H__ 11 12 /* 13 * gfx10_gb_reg.h 14 * 15 * Register Spec Release: 1.0 16 * 17 */ 18 19 // 20 // Make sure the necessary endian defines are there. 21 // 22 #if defined(LITTLEENDIAN_CPU) 23 #elif defined(BIGENDIAN_CPU) 24 #else 25 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 26 #endif 27 28 union GB_ADDR_CONFIG_GFX10 29 { 30 struct 31 { 32 #if defined(LITTLEENDIAN_CPU) 33 unsigned int NUM_PIPES : 3; 34 unsigned int PIPE_INTERLEAVE_SIZE : 3; 35 unsigned int MAX_COMPRESSED_FRAGS : 2; 36 unsigned int NUM_PKRS : 3; 37 unsigned int : 21; 38 #elif defined(BIGENDIAN_CPU) 39 unsigned int : 21; 40 unsigned int NUM_PKRS : 3; 41 unsigned int MAX_COMPRESSED_FRAGS : 2; 42 unsigned int PIPE_INTERLEAVE_SIZE : 3; 43 unsigned int NUM_PIPES : 3; 44 #endif 45 } bitfields, bits; 46 unsigned int u32All; 47 int i32All; 48 float f32All; 49 }; 50 51 #endif 52 53