1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <cbfs.h>
4 #include <console/console.h>
5 #include <memory_info.h>
6 #include <spd_bin.h>
7 #include <string.h>
8 #include <device/dram/ddr3.h>
9
dump_spd_info(struct spd_block * blk)10 void dump_spd_info(struct spd_block *blk)
11 {
12 u8 i;
13
14 for (i = 0; i < CONFIG_DIMM_MAX; i++)
15 if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) {
16 printk(BIOS_DEBUG, "SPD @ 0x%02X\n", blk->addr_map[i]);
17 print_spd_info(blk->spd_array[i]);
18 }
19 }
20
mainboard_get_dram_part_num(void)21 const char * __weak mainboard_get_dram_part_num(void)
22 {
23 /* Default weak implementation, no need to override part number. */
24 return NULL;
25 }
26
use_ddr4_params(int dram_type)27 static bool use_ddr4_params(int dram_type)
28 {
29 switch (dram_type) {
30 case SPD_DRAM_DDR3:
31 case SPD_DRAM_LPDDR3_INTEL:
32 return false;
33 /* Below DDR type share the same attributes */
34 case SPD_DRAM_LPDDR3_JEDEC:
35 case SPD_DRAM_DDR4:
36 case SPD_DRAM_DDR5:
37 case SPD_DRAM_LPDDR5:
38 case SPD_DRAM_LPDDR5X:
39 case SPD_DRAM_LPDDR4:
40 case SPD_DRAM_LPDDR4X:
41 return true;
42 default:
43 printk(BIOS_NOTICE, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
44 dram_type, __func__);
45 return true;
46 }
47 }
48
spd_get_module_type_string(int dram_type)49 static const char *spd_get_module_type_string(int dram_type)
50 {
51 switch (dram_type) {
52 case SPD_DRAM_DDR3:
53 return "DDR3";
54 case SPD_DRAM_LPDDR3_INTEL:
55 case SPD_DRAM_LPDDR3_JEDEC:
56 return "LPDDR3";
57 case SPD_DRAM_DDR4:
58 return "DDR4";
59 case SPD_DRAM_LPDDR4:
60 return "LPDDR4";
61 case SPD_DRAM_LPDDR4X:
62 return "LPDDR4X";
63 case SPD_DRAM_DDR5:
64 return "DDR5";
65 case SPD_DRAM_LPDDR5:
66 return "LPDDR5";
67 case SPD_DRAM_LPDDR5X:
68 return "LPDDR5X";
69 }
70 return "UNKNOWN";
71 }
72
spd_get_banks(const uint8_t spd[],int dram_type)73 static int spd_get_banks(const uint8_t spd[], int dram_type)
74 {
75 static const int ddr3_banks[4] = { 8, 16, 32, 64 };
76 static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
77 int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
78
79 if (use_ddr4_params(dram_type)) {
80 if (index >= ARRAY_SIZE(ddr4_banks))
81 return -1;
82 return ddr4_banks[index];
83 } else {
84 if (index >= ARRAY_SIZE(ddr3_banks))
85 return -1;
86 return ddr3_banks[index];
87 }
88 }
89
spd_get_capmb(const uint8_t spd[])90 static int spd_get_capmb(const uint8_t spd[])
91 {
92 static const int spd_capmb[13] = { 1, 2, 4, 8, 16, 32, 64,
93 128, 48, 96, 12, 24, 72 };
94 int index = spd[SPD_DENSITY_BANKS] & 0xf;
95 if (index >= ARRAY_SIZE(spd_capmb))
96 return -1;
97 return spd_capmb[index] * 256;
98 }
99
spd_get_rows(const uint8_t spd[])100 static int spd_get_rows(const uint8_t spd[])
101 {
102 static const int spd_rows[7] = { 12, 13, 14, 15, 16, 17, 18 };
103 int index = (spd[SPD_ADDRESSING] >> 3) & 7;
104 if (index >= ARRAY_SIZE(spd_rows))
105 return -1;
106 return spd_rows[index];
107 }
108
spd_get_cols(const uint8_t spd[])109 static int spd_get_cols(const uint8_t spd[])
110 {
111 static const int spd_cols[4] = { 9, 10, 11, 12 };
112 int index = spd[SPD_ADDRESSING] & 7;
113 if (index >= ARRAY_SIZE(spd_cols))
114 return -1;
115 return spd_cols[index];
116 }
117
spd_get_ranks(const uint8_t spd[],int dram_type)118 static int spd_get_ranks(const uint8_t spd[], int dram_type)
119 {
120 static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
121 int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
122 : DDR3_ORGANIZATION;
123 int index = (spd[organ_offset] >> 3) & 7;
124 if (index >= ARRAY_SIZE(spd_ranks))
125 return -1;
126 return spd_ranks[index];
127 }
128
spd_get_devw(const uint8_t spd[],int dram_type)129 static int spd_get_devw(const uint8_t spd[], int dram_type)
130 {
131 static const int spd_devw[4] = { 4, 8, 16, 32 };
132 int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
133 : DDR3_ORGANIZATION;
134 int index = spd[organ_offset] & 7;
135 if (index >= ARRAY_SIZE(spd_devw))
136 return -1;
137 return spd_devw[index];
138 }
139
spd_get_busw(const uint8_t spd[],int dram_type)140 static int spd_get_busw(const uint8_t spd[], int dram_type)
141 {
142 static const int spd_busw[4] = { 8, 16, 32, 64 };
143 int busw_offset = use_ddr4_params(dram_type) ? DDR4_BUS_DEV_WIDTH
144 : DDR3_BUS_DEV_WIDTH;
145 int index = spd[busw_offset] & 7;
146 if (index >= ARRAY_SIZE(spd_busw))
147 return -1;
148 return spd_busw[index];
149 }
150
spd_get_name(const uint8_t spd[],int type,const char ** spd_name,size_t * len)151 static void spd_get_name(const uint8_t spd[], int type, const char **spd_name, size_t *len)
152 {
153 *spd_name = mainboard_get_dram_part_num();
154 if (*spd_name != NULL) {
155 *len = strlen(*spd_name);
156 return;
157 }
158
159 switch (type) {
160 case SPD_DRAM_DDR3:
161 *spd_name = (const char *) &spd[DDR3_SPD_PART_OFF];
162 *len = DDR3_SPD_PART_LEN;
163 break;
164 case SPD_DRAM_LPDDR3_INTEL:
165 *spd_name = (const char *) &spd[LPDDR3_SPD_PART_OFF];
166 *len = LPDDR3_SPD_PART_LEN;
167 break;
168 /* LPDDR3, LPDDR4 and DDR4 have same part number offset and length */
169 case SPD_DRAM_LPDDR3_JEDEC:
170 case SPD_DRAM_DDR4:
171 case SPD_DRAM_DDR5:
172 case SPD_DRAM_LPDDR5:
173 case SPD_DRAM_LPDDR4:
174 case SPD_DRAM_LPDDR4X:
175 if (spd[DDR4_SPD_PART_OFF]) {
176 *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF];
177 *len = DDR4_SPD_PART_LEN;
178 }
179 break;
180 default:
181 *len = 0;
182 break;
183 }
184 }
185
print_spd_info(uint8_t spd[])186 void print_spd_info(uint8_t spd[])
187 {
188 const char *nameptr = NULL;
189 size_t len;
190 int type = spd[SPD_DRAM_TYPE];
191 int banks = spd_get_banks(spd, type);
192 int capmb = spd_get_capmb(spd);
193 int rows = spd_get_rows(spd);
194 int cols = spd_get_cols(spd);
195 int ranks = spd_get_ranks(spd, type);
196 int devw = spd_get_devw(spd, type);
197 int busw = spd_get_busw(spd, type);
198
199 /* Module type */
200 printk(BIOS_INFO, "SPD: module type is %s\n",
201 spd_get_module_type_string(type));
202 /* Module Part Number */
203 spd_get_name(spd, type, &nameptr, &len);
204 if (nameptr)
205 printk(BIOS_INFO, "SPD: module part number is %.*s\n", (int) len, nameptr);
206
207 printk(BIOS_INFO,
208 "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
209 banks, ranks, rows, cols, capmb);
210 printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
211 devw, busw);
212
213 if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
214 /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
215 printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
216 capmb / 8 * busw / devw * ranks);
217 }
218 }
219
spd_cbfs_map(u8 spd_index)220 uintptr_t spd_cbfs_map(u8 spd_index)
221 {
222 enum cbfs_type cbfs_type = CBFS_TYPE_SPD;
223 size_t size;
224
225 void *map = cbfs_type_map("spd.bin", &size, &cbfs_type);
226 if (!map || size < (spd_index + 1) * CONFIG_DIMM_SPD_SIZE)
227 return 0;
228
229 return (uintptr_t)map + spd_index * CONFIG_DIMM_SPD_SIZE;
230 }
231
232 #if CONFIG_DIMM_SPD_SIZE == 128
read_ddr3_spd_from_cbfs(u8 * buf,int idx)233 int read_ddr3_spd_from_cbfs(u8 *buf, int idx)
234 {
235 const int SPD_CRC_HI = 127;
236 const int SPD_CRC_LO = 126;
237
238 char *spd_file;
239 size_t spd_file_len = 0;
240 size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;
241
242 spd_file = cbfs_map("spd.bin", &spd_file_len);
243 if (!spd_file)
244 printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
245 if (spd_file_len < min_len)
246 printk(BIOS_EMERG, "Missing SPD data.");
247 if (!spd_file || spd_file_len < min_len)
248 return -1;
249
250 memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE),
251 CONFIG_DIMM_SPD_SIZE);
252 cbfs_unmap(spd_file);
253
254 u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);
255
256 if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
257 || (buf[SPD_CRC_LO] != (crc & 0xff))
258 || (buf[SPD_CRC_HI] != (crc >> 8))) {
259 printk(BIOS_WARNING,
260 "SPD CRC %02x%02x is invalid, should be %04x\n",
261 buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc);
262 buf[SPD_CRC_LO] = crc & 0xff;
263 buf[SPD_CRC_HI] = crc >> 8;
264 u16 i;
265 printk(BIOS_WARNING, "\nDisplay the SPD");
266 for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) {
267 if ((i % 16) == 0x00)
268 printk(BIOS_WARNING, "\n%02x: ", i);
269 printk(BIOS_WARNING, "%02x ", buf[i]);
270 }
271 printk(BIOS_WARNING, "\n");
272 }
273 return 0;
274 }
275 #endif
276