1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _INTEL_ME_H 4 #define _INTEL_ME_H 5 6 #include <device/device.h> 7 #include <types.h> 8 9 #define ME_RETRY 100000 /* 1 second */ 10 #define ME_DELAY 10 /* 10 us */ 11 12 /* 13 * Management Engine PCI registers 14 */ 15 16 #define PCI_CPU_DEVICE PCI_DEV(0,0,0) 17 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ 18 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ 19 20 #define PCI_ME_HFS 0x40 21 #define ME_HFS_CWS_RESET 0 22 #define ME_HFS_CWS_INIT 1 23 #define ME_HFS_CWS_REC 2 24 #define ME_HFS_CWS_NORMAL 5 25 #define ME_HFS_CWS_WAIT 6 26 #define ME_HFS_CWS_TRANS 7 27 #define ME_HFS_CWS_INVALID 8 28 #define ME_HFS_STATE_PREBOOT 0 29 #define ME_HFS_STATE_M0_UMA 1 30 #define ME_HFS_STATE_M3 4 31 #define ME_HFS_STATE_M0 5 32 #define ME_HFS_STATE_BRINGUP 6 33 #define ME_HFS_STATE_ERROR 7 34 #define ME_HFS_ERROR_NONE 0 35 #define ME_HFS_ERROR_UNCAT 1 36 #define ME_HFS_ERROR_IMAGE 3 37 #define ME_HFS_ERROR_DEBUG 4 38 #define ME_HFS_MODE_NORMAL 0 39 #define ME_HFS_MODE_DEBUG 2 40 #define ME_HFS_MODE_DIS 3 41 #define ME_HFS_MODE_OVER_JMPR 4 42 #define ME_HFS_MODE_OVER_MEI 5 43 #define ME_HFS_BIOS_DRAM_ACK 1 44 #define ME_HFS_ACK_NO_DID 0 45 #define ME_HFS_ACK_RESET 1 46 #define ME_HFS_ACK_PWR_CYCLE 2 47 #define ME_HFS_ACK_S3 3 48 #define ME_HFS_ACK_S4 4 49 #define ME_HFS_ACK_S5 5 50 #define ME_HFS_ACK_GBL_RESET 6 51 #define ME_HFS_ACK_CONTINUE 7 52 53 union me_hfs { 54 struct __packed { 55 u32 working_state: 4; 56 u32 mfg_mode: 1; 57 u32 fpt_bad: 1; 58 u32 operation_state: 3; 59 u32 fw_init_complete: 1; 60 u32 ft_bup_ld_flr: 1; 61 u32 update_in_progress: 1; 62 u32 error_code: 4; 63 u32 operation_mode: 4; 64 u32 reserved: 4; 65 u32 boot_options_present: 1; 66 u32 ack_data: 3; 67 u32 bios_msg_ack: 4; 68 }; 69 u32 raw; 70 }; 71 72 #define PCI_ME_UMA 0x44 73 74 union me_uma { 75 struct __packed { 76 u32 size: 6; 77 u32 reserved_1: 10; 78 u32 valid: 1; 79 u32 reserved_0: 14; 80 u32 set_to_one: 1; 81 }; 82 u32 raw; 83 }; 84 85 #define PCI_ME_H_GS 0x4c 86 #define ME_INIT_DONE 1 87 #define ME_INIT_STATUS_SUCCESS 0 88 #define ME_INIT_STATUS_NOMEM 1 89 #define ME_INIT_STATUS_ERROR 2 90 #define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ 91 92 union me_did { 93 struct __packed { 94 u32 uma_base: 16; 95 u32 reserved: 7; 96 u32 rapid_start: 1; 97 u32 status: 4; 98 u32 init_done: 4; 99 }; 100 u32 raw; 101 }; 102 103 /* 104 * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according 105 * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature. 106 */ 107 #define PCI_ME_HFS2 0x48 108 /* Infrastructure Progress Values */ 109 #define ME_HFS2_PHASE_ROM 0 110 #define ME_HFS2_PHASE_BUP 1 111 #define ME_HFS2_PHASE_UKERNEL 2 112 #define ME_HFS2_PHASE_POLICY 3 113 #define ME_HFS2_PHASE_MODULE_LOAD 4 114 #define ME_HFS2_PHASE_UNKNOWN 5 115 #define ME_HFS2_PHASE_HOST_COMM 6 116 /* Current State - Based on Infra Progress values. */ 117 /* ROM State */ 118 #define ME_HFS2_STATE_ROM_BEGIN 0 119 #define ME_HFS2_STATE_ROM_DISABLE 6 120 /* BUP State */ 121 #define ME_HFS2_STATE_BUP_INIT 0 122 #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 123 #define ME_HFS2_STATE_BUP_FLOW_DET 4 124 #define ME_HFS2_STATE_BUP_VSCC_ERR 8 125 #define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa 126 #define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb 127 #define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd 128 #define ME_HFS2_STATE_BUP_M3 0x11 129 #define ME_HFS2_STATE_BUP_M0 0x12 130 #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 131 #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 132 #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 133 #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 134 #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c 135 #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f 136 #define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 137 #define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 138 #define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 139 #define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 140 #define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 141 #define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 142 #define ME_HFS2_STATE_BUP_M0_CLK 0x26 143 #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 144 #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 145 #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 146 /* Policy Module State */ 147 #define ME_HFS2_STATE_POLICY_ENTRY 0 148 #define ME_HFS2_STATE_POLICY_RCVD_S3 3 149 #define ME_HFS2_STATE_POLICY_RCVD_S4 4 150 #define ME_HFS2_STATE_POLICY_RCVD_S5 5 151 #define ME_HFS2_STATE_POLICY_RCVD_UPD 6 152 #define ME_HFS2_STATE_POLICY_RCVD_PCR 7 153 #define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 154 #define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 155 #define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa 156 #define ME_HFS2_STATE_POLICY_RCVD_DID 0xb 157 #define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc 158 #define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd 159 #define ME_HFS2_STATE_POLICY_FPB_ERR 0xe 160 #define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf 161 #define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 162 /* Current PM Event Values */ 163 #define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 164 #define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 165 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 166 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 167 #define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 168 #define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 169 #define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 170 #define ME_HFS2_PMEVENT_S0MO_SXM3 7 171 #define ME_HFS2_PMEVENT_SXM3_S0M0 8 172 #define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 173 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa 174 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb 175 #define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc 176 177 union me_hfs2 { 178 struct __packed { 179 u32 bist_in_progress: 1; 180 u32 icc_prog_sts: 2; 181 u32 invoke_mebx: 1; 182 u32 cpu_replaced_sts: 1; 183 u32 mbp_rdy: 1; 184 u32 mfs_failure: 1; 185 u32 warm_reset_request: 1; 186 u32 cpu_replaced_valid: 1; 187 u32 reserved: 2; 188 u32 fw_upd_ipu: 1; 189 u32 reserved2: 1; 190 u32 mbp_cleared: 1; 191 u32 reserved3: 2; 192 u32 current_state: 8; 193 u32 current_pmevent: 4; 194 u32 progress_code: 4; 195 }; 196 u32 raw; 197 }; 198 199 #define PCI_ME_H_GS2 0x70 200 #define PCI_ME_MBP_GIVE_UP 0x01 201 202 #define PCI_ME_HERES 0xbc 203 #define PCI_ME_EXT_SHA1 0x00 204 #define PCI_ME_EXT_SHA256 0x02 205 #define PCI_ME_HER(x) (0xc0+(4*(x))) 206 207 union me_heres { 208 struct __packed { 209 u32 extend_reg_algorithm: 4; 210 u32 reserved: 26; 211 u32 extend_feature_present: 1; 212 u32 extend_reg_valid: 1; 213 }; 214 u32 raw; 215 }; 216 217 /* 218 * Management Engine MEI registers 219 */ 220 221 #define MEI_H_CB_WW 0x00 222 #define MEI_H_CSR 0x04 223 #define MEI_ME_CB_RW 0x08 224 #define MEI_ME_CSR_HA 0x0c 225 226 union mei_csr { 227 struct __packed { 228 u32 interrupt_enable: 1; 229 u32 interrupt_status: 1; 230 u32 interrupt_generate: 1; 231 u32 ready: 1; 232 u32 reset: 1; 233 u32 reserved: 3; 234 u32 buffer_read_ptr: 8; 235 u32 buffer_write_ptr: 8; 236 u32 buffer_depth: 8; 237 }; 238 u32 raw; 239 }; 240 241 #define MEI_ADDRESS_CORE 0x01 242 #define MEI_ADDRESS_AMT 0x02 243 #define MEI_ADDRESS_RESERVED 0x03 244 #define MEI_ADDRESS_WDT 0x04 245 #define MEI_ADDRESS_MKHI 0x07 246 #define MEI_ADDRESS_ICC 0x08 247 #define MEI_ADDRESS_THERMAL 0x09 248 249 #define MEI_HOST_ADDRESS 0 250 251 union mei_header { 252 struct __packed { 253 u32 client_address: 8; 254 u32 host_address: 8; 255 u32 length: 9; 256 u32 reserved: 6; 257 u32 is_complete: 1; 258 }; 259 u32 raw; 260 }; 261 262 #define MKHI_GROUP_ID_CBM 0x00 263 #define MKHI_GROUP_ID_FWCAPS 0x03 264 #define MKHI_GROUP_ID_MDES 0x08 265 #define MKHI_GROUP_ID_GEN 0xff 266 267 #define MKHI_GLOBAL_RESET 0x0b 268 269 #define MKHI_FWCAPS_GET_RULE 0x02 270 271 #define MKHI_MDES_ENABLE 0x09 272 273 #define MKHI_GET_FW_VERSION 0x02 274 #define MKHI_END_OF_POST 0x0c 275 #define MKHI_FEATURE_OVERRIDE 0x14 276 277 struct mkhi_header { 278 u32 group_id: 8; 279 u32 command: 7; 280 u32 is_response: 1; 281 u32 reserved: 8; 282 u32 result: 8; 283 } __packed; 284 285 struct me_fw_version { 286 u16 code_minor; 287 u16 code_major; 288 u16 code_build_number; 289 u16 code_hot_fix; 290 u16 recovery_minor; 291 u16 recovery_major; 292 u16 recovery_build_number; 293 u16 recovery_hot_fix; 294 } __packed; 295 296 /* ICC Messages */ 297 #define ICC_SET_CLOCK_ENABLES 0x3 298 #define ICC_API_VERSION_LYNXPOINT 0x00030000 299 300 struct icc_header { 301 u32 api_version; 302 u32 icc_command; 303 u32 icc_status; 304 u32 length; 305 u32 reserved; 306 } __packed; 307 308 struct icc_clock_enables_msg { 309 u32 clock_enables; 310 u32 clock_mask; 311 u32 no_response: 1; 312 u32 reserved: 31; 313 } __packed; 314 315 #define HECI_EOP_STATUS_SUCCESS 0x0 316 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 317 318 #define CBM_RR_GLOBAL_RESET 0x01 319 320 #define GLOBAL_RESET_BIOS_MRC 0x01 321 #define GLOBAL_RESET_BIOS_POST 0x02 322 #define GLOBAL_RESET_MEBX 0x03 323 324 struct me_global_reset { 325 u8 request_origin; 326 u8 reset_type; 327 } __packed; 328 329 enum me_bios_path { 330 ME_NORMAL_BIOS_PATH, 331 ME_S3WAKE_BIOS_PATH, 332 ME_ERROR_BIOS_PATH, 333 ME_RECOVERY_BIOS_PATH, 334 ME_DISABLE_BIOS_PATH, 335 ME_FIRMWARE_UPDATE_BIOS_PATH, 336 }; 337 338 /* Defined in me_status.c for both romstage and ramstage */ 339 void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2); 340 341 void intel_early_me_status(void); 342 int intel_early_me_init(void); 343 bool intel_early_me_cpu_replacement_check(void); 344 int intel_early_me_uma_size(void); 345 int intel_early_me_init_done(u8 status); 346 347 void intel_me_finalize(struct device *dev); 348 349 /* 350 * ME to BIOS Payload Datastructures and definitions. The ordering of the 351 * structures follows the ordering in the ME9 BWG. 352 */ 353 354 #define MBP_APPID_KERNEL 1 355 #define MBP_APPID_INTEL_AT 3 356 #define MBP_APPID_HWA 4 357 #define MBP_APPID_ICC 5 358 #define MBP_APPID_NFC 6 359 /* Kernel items: */ 360 #define MBP_KERNEL_FW_VER_ITEM 1 361 #define MBP_KERNEL_FW_CAP_ITEM 2 362 #define MBP_KERNEL_ROM_BIST_ITEM 3 363 #define MBP_KERNEL_PLAT_KEY_ITEM 4 364 #define MBP_KERNEL_FW_TYPE_ITEM 5 365 #define MBP_KERNEL_MFS_FAILURE_ITEM 6 366 #define MBP_KERNEL_PLAT_TIME_ITEM 7 367 /* Intel AT items: */ 368 #define MBP_INTEL_AT_STATE_ITEM 1 369 /* ICC Items: */ 370 #define MBP_ICC_PROFILE_ITEM 1 371 /* HWA Items: */ 372 #define MBP_HWA_REQUEST_ITEM 1 373 /* NFC Items: */ 374 #define MBP_NFC_SUPPORT_DATA_ITEM 1 375 376 #define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) 377 #define MBP_IDENT(appid, item) \ 378 MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) 379 380 union mbp_header { 381 struct __packed { 382 u32 mbp_size : 8; 383 u32 num_entries : 8; 384 u32 rsvd : 16; 385 }; 386 u32 raw; 387 }; 388 389 struct mbp_item_header { 390 u32 app_id : 8; 391 u32 item_id : 8; 392 u32 length : 8; 393 u32 rsvd : 8; 394 } __packed; 395 396 struct mbp_fw_version_name { 397 u32 major_version : 16; 398 u32 minor_version : 16; 399 u32 hotfix_version : 16; 400 u32 build_version : 16; 401 } __packed; 402 403 struct mbp_mefwcaps { 404 u32 full_net : 1; 405 u32 std_net : 1; 406 u32 manageability : 1; 407 u32 reserved_2 : 2; 408 u32 intel_at : 1; 409 u32 intel_cls : 1; 410 u32 reserved : 3; 411 u32 intel_mpc : 1; 412 u32 icc_over_clocking : 1; 413 u32 pavp : 1; 414 u32 reserved_1 : 4; 415 u32 ipv6 : 1; 416 u32 kvm : 1; 417 u32 och : 1; 418 u32 vlan : 1; 419 u32 tls : 1; 420 u32 reserved_4 : 1; 421 u32 wlan : 1; 422 u32 reserved_5 : 8; 423 } __packed; 424 425 struct mbp_rom_bist_data { 426 u16 device_id; 427 u16 fuse_test_flags; 428 u32 umchid[4]; 429 } __packed; 430 431 struct mbp_platform_key { 432 u32 key[8]; 433 }; 434 435 struct mbp_me_firmware_type { 436 u32 mobile: 1; 437 u32 desktop: 1; 438 u32 server: 1; 439 u32 workstation: 1; 440 u32 corporate: 1; 441 u32 consumer: 1; 442 u32 regular_super_sku: 1; 443 u32 rsvd: 1; 444 u32 image_type: 4; 445 u32 brand: 4; 446 u32 rsvd1: 16; 447 } __packed; 448 449 struct mbp_plat_type { 450 struct mbp_me_firmware_type rule_data; 451 u8 available; 452 }; 453 454 struct icc_address_mask { 455 u16 icc_start_address; 456 u16 mask; 457 } __packed; 458 459 struct mbp_icc_profile { 460 u8 num_icc_profiles; 461 u8 icc_profile_soft_strap; 462 u8 icc_profile_index; 463 u8 reserved; 464 u32 icc_reg_bundles; 465 struct icc_address_mask icc_address_mask[]; 466 } __packed; 467 468 struct tdt_state_flag { 469 u16 lock_state : 1; 470 u16 authenticate_module : 1; 471 u16 s3authentication : 1; 472 u16 flash_wear_out : 1; 473 u16 flash_variable_security : 1; 474 u16 reserved : 11; 475 } __packed; 476 477 struct mbp_at_state { 478 u8 state; 479 u8 last_theft_trigger; 480 struct tdt_state_flag flags; 481 } __packed; 482 483 struct mbp_plat_time { 484 u32 wake_event_mrst_time_ms; 485 u32 mrst_pltrst_time_ms; 486 u32 pltrst_cpurst_time_ms; 487 } __packed; 488 489 struct mbp_nfc_data { 490 u32 device_type : 2; 491 u32 reserved : 30; 492 } __packed; 493 494 struct me_bios_payload { 495 struct mbp_fw_version_name *fw_version_name; 496 struct mbp_mefwcaps *fw_capabilities; 497 struct mbp_rom_bist_data *rom_bist_data; 498 struct mbp_platform_key *platform_key; 499 struct mbp_plat_type *fw_plat_type; 500 struct mbp_icc_profile *icc_profile; 501 struct mbp_at_state *at_state; 502 u32 *mfsintegrity; 503 struct mbp_plat_time *plat_time; 504 struct mbp_nfc_data *nfc_data; 505 }; 506 507 struct me_fwcaps { 508 u32 id; 509 u8 length; 510 struct mbp_mefwcaps caps_sku; 511 u8 reserved[3]; 512 } __packed; 513 514 #endif /* _INTEL_ME_H */ 515