1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef INTEL_LYNXPOINT_LP_GPIO_H 4 #define INTEL_LYNXPOINT_LP_GPIO_H 5 6 #include <stdint.h> 7 8 /* LynxPoint LP GPIOBASE Registers */ 9 #define GPIO_OWNER(set) (0x00 + ((set) * 4)) 10 #define GPIO_PIRQ_APIC_EN 0x10 11 #define GPIO_BLINK 0x18 12 #define GPIO_SER_BLINK 0x1c 13 #define GPIO_SER_BLINK_CS 0x20 14 #define GPIO_SER_BLINK_DATA 0x24 15 #define GPIO_ROUTE(set) (0x30 + ((set) * 4)) 16 #define GPIO_RESET(set) (0x60 + ((set) * 4)) 17 #define GPIO_GLOBAL_CONFIG 0x7c 18 #define GPIO_IRQ_IS(set) (0x80 + ((set) * 4)) 19 #define GPIO_IRQ_IE(set) (0x90 + ((set) * 4)) 20 #define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8)) 21 #define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8)) 22 23 #define MAX_GPIO_NUMBER 94 /* zero based */ 24 #define GPIO_LIST_END 0xffffffff 25 26 /* conf0 */ 27 28 #define GPIO_MODE_NATIVE (0 << 0) 29 #define GPIO_MODE_GPIO (1 << 0) 30 31 #define GPIO_DIR_OUTPUT (0 << 2) 32 #define GPIO_DIR_INPUT (1 << 2) 33 34 #define GPIO_NO_INVERT (0 << 3) 35 #define GPIO_INVERT (1 << 3) 36 37 #define GPIO_IRQ_EDGE (0 << 4) 38 #define GPIO_IRQ_LEVEL (1 << 4) 39 40 #define GPI_LEVEL (1 << 30) 41 42 #define GPO_LEVEL_SHIFT 31 43 #define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT) 44 #define GPO_LEVEL_LOW (0 << GPO_LEVEL_SHIFT) 45 #define GPO_LEVEL_HIGH (1 << GPO_LEVEL_SHIFT) 46 47 /* conf1 */ 48 49 #define GPIO_PULL_NONE (0 << 0) 50 #define GPIO_PULL_DOWN (1 << 0) 51 #define GPIO_PULL_UP (2 << 0) 52 53 #define GPIO_SENSE_ENABLE (0 << 2) 54 #define GPIO_SENSE_DISABLE (1 << 2) 55 56 /* owner */ 57 58 #define GPIO_OWNER_ACPI 0 59 #define GPIO_OWNER_GPIO 1 60 61 /* route */ 62 63 #define GPIO_ROUTE_SCI 0 64 #define GPIO_ROUTE_SMI 1 65 66 /* irqen */ 67 68 #define GPIO_IRQ_DISABLE 0 69 #define GPIO_IRQ_ENABLE 1 70 71 /* blink */ 72 73 #define GPO_NO_BLINK 0 74 #define GPO_BLINK 1 75 76 /* reset */ 77 78 #define GPIO_RESET_PWROK 0 79 #define GPIO_RESET_RSMRST 1 80 81 /* pirq route to io-apic */ 82 83 #define GPIO_PIRQ_APIC_MASK 0 84 #define GPIO_PIRQ_APIC_ROUTE 1 85 86 #define LP_GPIO_END \ 87 { .conf0 = GPIO_LIST_END } 88 89 #define LP_GPIO_NATIVE \ 90 { .conf0 = GPIO_MODE_NATIVE } 91 92 #define LP_GPIO_UNUSED \ 93 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ 94 .owner = GPIO_OWNER_GPIO, \ 95 .conf1 = GPIO_SENSE_DISABLE } 96 97 #define LP_GPIO_ACPI_SCI \ 98 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ 99 .owner = GPIO_OWNER_ACPI, \ 100 .route = GPIO_ROUTE_SCI } 101 102 #define LP_GPIO_ACPI_SMI \ 103 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ 104 .owner = GPIO_OWNER_ACPI, \ 105 .route = GPIO_ROUTE_SMI } 106 107 #define LP_GPIO_INPUT \ 108 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ 109 .owner = GPIO_OWNER_GPIO } 110 111 #define LP_GPIO_INPUT_INVERT \ 112 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ 113 .owner = GPIO_OWNER_GPIO } 114 115 #define LP_GPIO_IRQ_EDGE \ 116 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \ 117 .owner = GPIO_OWNER_GPIO, \ 118 .irqen = GPIO_IRQ_ENABLE } 119 120 #define LP_GPIO_IRQ_LEVEL \ 121 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \ 122 .owner = GPIO_OWNER_GPIO, \ 123 .irqen = GPIO_IRQ_ENABLE } 124 125 #define LP_GPIO_PIRQ \ 126 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ 127 .owner = GPIO_OWNER_GPIO, \ 128 .pirq = GPIO_PIRQ_APIC_ROUTE } 129 130 #define LP_GPIO_PIRQ_INVERT \ 131 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ 132 .owner = GPIO_OWNER_GPIO, \ 133 .pirq = GPIO_PIRQ_APIC_ROUTE } 134 135 #define LP_GPIO_OUT_HIGH \ 136 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \ 137 .owner = GPIO_OWNER_GPIO, \ 138 .conf1 = GPIO_SENSE_DISABLE } 139 140 #define LP_GPIO_OUT_LOW \ 141 { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \ 142 .owner = GPIO_OWNER_GPIO, \ 143 .conf1 = GPIO_SENSE_DISABLE } 144 145 struct pch_lp_gpio_map { 146 u8 gpio; 147 u32 conf0; 148 u32 conf1; 149 u8 owner; 150 u8 route; 151 u8 irqen; 152 u8 reset; 153 u8 blink; 154 u8 pirq; 155 } __packed; 156 157 /* Configure GPIOs with mainboard provided settings */ 158 void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); 159 160 /* Get GPIO pin value */ 161 int get_gpio(int gpio_num); 162 163 /* Set GPIO pin value */ 164 void set_gpio(int gpio_num, int value); 165 166 /* Return non-zero if gpio is set to native function. 0 otherwise. */ 167 int gpio_is_native(int gpio_num); 168 169 /* 170 * Get a number comprised of multiple GPIO values. gpio_num_array points to 171 * the array of gpio pin numbers to scan, terminated by -1. 172 */ 173 unsigned int get_gpios(const int *gpio_num_array); 174 175 extern const struct pch_lp_gpio_map mainboard_lp_gpio_map[]; 176 177 #endif 178