1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _INTEL_ME_H 4 #define _INTEL_ME_H 5 6 #include <types.h> 7 8 #define ME_RETRY 100000 /* 1 second */ 9 #define ME_DELAY 10 /* 10 us */ 10 11 /* 12 * Management Engine PCI registers 13 */ 14 15 #define PCI_CPU_DEVICE PCI_DEV(0,0,0) 16 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ 17 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ 18 19 #define PCI_ME_HFS 0x40 20 #define ME_HFS_CWS_RESET 0 21 #define ME_HFS_CWS_INIT 1 22 #define ME_HFS_CWS_REC 2 23 #define ME_HFS_CWS_NORMAL 5 24 #define ME_HFS_CWS_WAIT 6 25 #define ME_HFS_CWS_TRANS 7 26 #define ME_HFS_CWS_INVALID 8 27 #define ME_HFS_STATE_PREBOOT 0 28 #define ME_HFS_STATE_M0_UMA 1 29 #define ME_HFS_STATE_M3 4 30 #define ME_HFS_STATE_M0 5 31 #define ME_HFS_STATE_BRINGUP 6 32 #define ME_HFS_STATE_ERROR 7 33 #define ME_HFS_ERROR_NONE 0 34 #define ME_HFS_ERROR_UNCAT 1 35 #define ME_HFS_ERROR_IMAGE 3 36 #define ME_HFS_ERROR_DEBUG 4 37 #define ME_HFS_MODE_NORMAL 0 38 #define ME_HFS_MODE_DEBUG 2 39 #define ME_HFS_MODE_DIS 3 40 #define ME_HFS_MODE_OVER_JMPR 4 41 #define ME_HFS_MODE_OVER_MEI 5 42 #define ME_HFS_BIOS_DRAM_ACK 1 43 #define ME_HFS_ACK_NO_DID 0 44 #define ME_HFS_ACK_RESET 1 45 #define ME_HFS_ACK_PWR_CYCLE 2 46 #define ME_HFS_ACK_S3 3 47 #define ME_HFS_ACK_S4 4 48 #define ME_HFS_ACK_S5 5 49 #define ME_HFS_ACK_GBL_RESET 6 50 #define ME_HFS_ACK_CONTINUE 7 51 52 struct me_hfs { 53 u32 working_state: 4; 54 u32 mfg_mode: 1; 55 u32 fpt_bad: 1; 56 u32 operation_state: 3; 57 u32 fw_init_complete: 1; 58 u32 ft_bup_ld_flr: 1; 59 u32 update_in_progress: 1; 60 u32 error_code: 4; 61 u32 operation_mode: 4; 62 u32 reserved: 4; 63 u32 boot_options_present: 1; 64 u32 ack_data: 3; 65 u32 bios_msg_ack: 4; 66 } __packed; 67 68 #define PCI_ME_UMA 0x44 69 70 struct me_uma { 71 u32 size: 6; 72 u32 reserved_1: 10; 73 u32 valid: 1; 74 u32 reserved_0: 14; 75 u32 set_to_one: 1; 76 } __packed; 77 78 #define PCI_ME_H_GS 0x4c 79 #define ME_INIT_DONE 1 80 #define ME_INIT_STATUS_SUCCESS 0 81 #define ME_INIT_STATUS_NOMEM 1 82 #define ME_INIT_STATUS_ERROR 2 83 84 struct me_did { 85 u32 uma_base: 16; 86 u32 reserved: 8; 87 u32 status: 4; 88 u32 init_done: 4; 89 } __packed; 90 91 #define PCI_ME_GMES 0x48 92 #define ME_GMES_PHASE_ROM 0 93 #define ME_GMES_PHASE_BUP 1 94 #define ME_GMES_PHASE_UKERNEL 2 95 #define ME_GMES_PHASE_POLICY 3 96 #define ME_GMES_PHASE_MODULE 4 97 #define ME_GMES_PHASE_UNKNOWN 5 98 #define ME_GMES_PHASE_HOST 6 99 100 struct me_gmes { 101 u32 bist_in_prog : 1; 102 u32 icc_prog_sts : 2; 103 u32 invoke_mebx : 1; 104 u32 cpu_replaced_sts : 1; 105 u32 mbp_rdy : 1; 106 u32 mfs_failure : 1; 107 u32 warm_rst_req_for_df : 1; 108 u32 cpu_replaced_valid : 1; 109 u32 reserved_1 : 2; 110 u32 fw_upd_ipu : 1; 111 u32 reserved_2 : 4; 112 u32 current_state: 8; 113 u32 current_pmevent: 4; 114 u32 progress_code: 4; 115 } __packed; 116 117 #define PCI_ME_HERES 0xbc 118 #define PCI_ME_EXT_SHA1 0x00 119 #define PCI_ME_EXT_SHA256 0x02 120 #define PCI_ME_HER(x) (0xc0+(4*(x))) 121 122 struct me_heres { 123 u32 extend_reg_algorithm: 4; 124 u32 reserved: 26; 125 u32 extend_feature_present: 1; 126 u32 extend_reg_valid: 1; 127 } __packed; 128 129 /* 130 * Management Engine MEI registers 131 */ 132 133 #define MEI_H_CB_WW 0x00 134 #define MEI_H_CSR 0x04 135 #define MEI_ME_CB_RW 0x08 136 #define MEI_ME_CSR_HA 0x0c 137 138 struct mei_csr { 139 u32 interrupt_enable: 1; 140 u32 interrupt_status: 1; 141 u32 interrupt_generate: 1; 142 u32 ready: 1; 143 u32 reset: 1; 144 u32 reserved: 3; 145 u32 buffer_read_ptr: 8; 146 u32 buffer_write_ptr: 8; 147 u32 buffer_depth: 8; 148 } __packed; 149 150 #define MEI_ADDRESS_CORE 0x01 151 #define MEI_ADDRESS_AMT 0x02 152 #define MEI_ADDRESS_RESERVED 0x03 153 #define MEI_ADDRESS_WDT 0x04 154 #define MEI_ADDRESS_MKHI 0x07 155 #define MEI_ADDRESS_ICC 0x08 156 #define MEI_ADDRESS_THERMAL 0x09 157 158 #define MEI_HOST_ADDRESS 0 159 160 struct mei_header { 161 u32 client_address: 8; 162 u32 host_address: 8; 163 u32 length: 9; 164 u32 reserved: 6; 165 u32 is_complete: 1; 166 } __packed; 167 168 #define MKHI_GROUP_ID_CBM 0x00 169 #define MKHI_GROUP_ID_FWCAPS 0x03 170 #define MKHI_GROUP_ID_MDES 0x08 171 #define MKHI_GROUP_ID_GEN 0xff 172 173 #define MKHI_GLOBAL_RESET 0x0b 174 175 #define MKHI_FWCAPS_GET_RULE 0x02 176 177 #define MKHI_MDES_ENABLE 0x09 178 179 #define MKHI_GET_FW_VERSION 0x02 180 #define MKHI_SET_UMA 0x08 181 #define MKHI_END_OF_POST 0x0c 182 #define MKHI_FEATURE_OVERRIDE 0x14 183 184 struct mkhi_header { 185 u32 group_id: 8; 186 u32 command: 7; 187 u32 is_response: 1; 188 u32 reserved: 8; 189 u32 result: 8; 190 } __packed; 191 192 struct me_fw_version { 193 u16 code_minor; 194 u16 code_major; 195 u16 code_build_number; 196 u16 code_hot_fix; 197 u16 recovery_minor; 198 u16 recovery_major; 199 u16 recovery_build_number; 200 u16 recovery_hot_fix; 201 } __packed; 202 203 #define HECI_EOP_STATUS_SUCCESS 0x0 204 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 205 206 #define CBM_RR_GLOBAL_RESET 0x01 207 208 #define GLOBAL_RESET_BIOS_MRC 0x01 209 #define GLOBAL_RESET_BIOS_POST 0x02 210 #define GLOBAL_RESET_MEBX 0x03 211 212 struct me_global_reset { 213 u8 request_origin; 214 u8 reset_type; 215 } __packed; 216 217 typedef enum { 218 ME_NORMAL_BIOS_PATH, 219 ME_S3WAKE_BIOS_PATH, 220 ME_ERROR_BIOS_PATH, 221 ME_RECOVERY_BIOS_PATH, 222 ME_DISABLE_BIOS_PATH, 223 ME_FIRMWARE_UPDATE_BIOS_PATH, 224 } me_bios_path; 225 226 /* Defined in me_status.c for both romstage and ramstage */ 227 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); 228 229 void intel_early_me_status(void); 230 int intel_early_me_init(void); 231 int intel_early_me_uma_size(void); 232 int intel_early_me_init_done(u8 status); 233 234 void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size); 235 236 typedef struct { 237 u32 major_version : 16; 238 u32 minor_version : 16; 239 u32 hotfix_version : 16; 240 u32 build_version : 16; 241 } __packed mbp_fw_version_name; 242 243 typedef struct { 244 u8 num_icc_profiles; 245 u8 icc_profile_soft_strap; 246 u8 icc_profile_index; 247 u8 reserved; 248 u32 register_lock_mask[3]; 249 } __packed mbp_icc_profile; 250 251 typedef struct { 252 u32 full_net : 1; 253 u32 std_net : 1; 254 u32 manageability : 1; 255 u32 small_business : 1; 256 u32 l3manageability : 1; 257 u32 intel_at : 1; 258 u32 intel_cls : 1; 259 u32 reserved : 3; 260 u32 intel_mpc : 1; 261 u32 icc_over_clocking : 1; 262 u32 pavp : 1; 263 u32 reserved_1 : 4; 264 u32 ipv6 : 1; 265 u32 kvm : 1; 266 u32 och : 1; 267 u32 vlan : 1; 268 u32 tls : 1; 269 u32 reserved_4 : 1; 270 u32 wlan : 1; 271 u32 reserved_5 : 8; 272 } __packed mefwcaps_sku; 273 274 typedef struct { 275 u16 lock_state : 1; 276 u16 authenticate_module : 1; 277 u16 s3authentication : 1; 278 u16 flash_wear_out : 1; 279 u16 flash_variable_security : 1; 280 u16 wwan3gpresent : 1; 281 u16 wwan3goob : 1; 282 u16 reserved : 9; 283 } __packed tdt_state_flag; 284 285 typedef struct { 286 u8 state; 287 u8 last_theft_trigger; 288 tdt_state_flag flags; 289 } __packed tdt_state_info; 290 291 typedef struct { 292 u32 platform_target_usage_type : 4; 293 u32 platform_target_market_type : 2; 294 u32 super_sku : 1; 295 u32 reserved : 1; 296 u32 intel_me_fw_image_type : 4; 297 u32 platform_brand : 4; 298 u32 reserved_1 : 16; 299 } __packed platform_type_rule_data; 300 301 typedef struct { 302 mefwcaps_sku fw_capabilities; 303 u8 available; 304 } mbp_fw_caps; 305 306 typedef struct { 307 u16 device_id; 308 u16 fuse_test_flags; 309 u32 umchid[4]; 310 } __packed mbp_rom_bist_data; 311 312 typedef struct { 313 u32 key[8]; 314 } mbp_platform_key; 315 316 typedef struct { 317 platform_type_rule_data rule_data; 318 u8 available; 319 } mbp_plat_type; 320 321 typedef struct { 322 mbp_fw_version_name fw_version_name; 323 mbp_fw_caps fw_caps_sku; 324 mbp_rom_bist_data rom_bist_data; 325 mbp_platform_key platform_key; 326 mbp_plat_type fw_plat_type; 327 mbp_icc_profile icc_profile; 328 tdt_state_info at_state; 329 u32 mfsintegrity; 330 } me_bios_payload; 331 332 typedef struct { 333 u32 mbp_size : 8; 334 u32 num_entries : 8; 335 u32 rsvd : 16; 336 } __packed mbp_header; 337 338 typedef struct { 339 u32 app_id : 8; 340 u32 item_id : 8; 341 u32 length : 8; 342 u32 rsvd : 8; 343 } __packed mbp_item_header; 344 345 struct me_fwcaps { 346 u32 id; 347 u8 length; 348 mefwcaps_sku caps_sku; 349 u8 reserved[3]; 350 } __packed; 351 352 #endif /* _INTEL_ME_H */ 353