1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/pci.h>
5 #include <soc/pch_pci_devs.h>
6 #include <soc/xhci.h>
7 #include <types.h>
8
9 // XHCI register
10 #define SYS_BUS_CFG2 0x44
11
get_xhci_bar(void)12 static uint8_t *get_xhci_bar(void)
13 {
14 const struct resource *res;
15 res = probe_resource(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0);
16 if (!res) {
17 printk(BIOS_ERR, "XHCI BAR is not found\n");
18 return NULL;
19 }
20 return (void *)(uintptr_t)res->base;
21 }
22
write_usb_oc_mapping(const struct usb_oc_mapping * config,uint8_t pins)23 void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins)
24 {
25 uint8_t *mbar = get_xhci_bar();
26 uint8_t i;
27
28 if (mbar == NULL) {
29 printk(BIOS_ERR, "XHCI BAR is invalid, skip USB OC mapping configuration\n");
30 return;
31 }
32 for (i = 0; i < pins; i++)
33 write32(mbar + config[i].pin, config[i].port);
34 }
35
lock_oc_cfg(bool lock)36 void lock_oc_cfg(bool lock)
37 {
38 uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2);
39
40 if (lock)
41 cfg |= OCCFGDONE;
42 else
43 cfg &= ~(OCCFGDONE);
44 pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg);
45 }
46