1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef __TEGRA_DSI_H__
3 #define __TEGRA_DSI_H__
4
5 #include <device/mmio.h>
6
7 #define DSI_INCR_SYNCPT 0x00
8 #define DSI_INCR_SYNCPT_CONTROL 0x01
9 #define DSI_INCR_SYNCPT_ERROR 0x02
10 #define DSI_CTXSW 0x08
11 #define DSI_RD_DATA 0x09
12 #define DSI_WR_DATA 0x0a
13 #define DSI_POWER_CONTROL 0x0b
14 #define DSI_POWER_CONTROL_ENABLE (1 << 0)
15 #define DSI_INT_ENABLE 0x0c
16 #define DSI_INT_STATUS 0x0d
17 #define DSI_INT_MASK 0x0e
18 #define DSI_HOST_CONTROL 0x0f
19 #define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
20 #define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
21 #define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
22 #define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
23 #define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
24 #define DSI_HOST_CONTROL_RAW (1 << 6)
25 #define DSI_HOST_CONTROL_HS (1 << 5)
26 #define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
27 #define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
28 #define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
29 #define DSI_HOST_CONTROL_CS (1 << 1)
30 #define DSI_HOST_CONTROL_ECC (1 << 0)
31 #define DSI_CONTROL 0x10
32 #define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
33 #define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
34 #define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
35 #define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
36 #define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
37 #define DSI_CONTROL_DCS_ENABLE (1 << 3)
38 #define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
39 #define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
40 #define DSI_CONTROL_HOST_ENABLE (1 << 0)
41 #define DSI_SOL_DELAY 0x11
42 #define DSI_MAX_THRESHOLD 0x12
43 #define DSI_TRIGGER 0x13
44 #define DSI_TRIGGER_HOST (1 << 1)
45 #define DSI_TRIGGER_VIDEO (1 << 0)
46 #define DSI_TX_CRC 0x14
47 #define DSI_STATUS 0x15
48 #define DSI_STATUS_IDLE (1 << 10)
49 #define DSI_STATUS_UNDERFLOW (1 << 9)
50 #define DSI_STATUS_OVERFLOW (1 << 8)
51 #define DSI_INIT_SEQ_CONTROL 0x1a
52 #define DSI_INIT_SEQ_DATA_0 0x1b
53 #define DSI_INIT_SEQ_DATA_1 0x1c
54 #define DSI_INIT_SEQ_DATA_2 0x1d
55 #define DSI_INIT_SEQ_DATA_3 0x1e
56 #define DSI_INIT_SEQ_DATA_4 0x1f
57 #define DSI_INIT_SEQ_DATA_5 0x20
58 #define DSI_INIT_SEQ_DATA_6 0x21
59 #define DSI_INIT_SEQ_DATA_7 0x22
60 #define DSI_PKT_SEQ_0_LO 0x23
61 #define DSI_PKT_SEQ_0_HI 0x24
62 #define DSI_PKT_SEQ_1_LO 0x25
63 #define DSI_PKT_SEQ_1_HI 0x26
64 #define DSI_PKT_SEQ_2_LO 0x27
65 #define DSI_PKT_SEQ_2_HI 0x28
66 #define DSI_PKT_SEQ_3_LO 0x29
67 #define DSI_PKT_SEQ_3_HI 0x2a
68 #define DSI_PKT_SEQ_4_LO 0x2b
69 #define DSI_PKT_SEQ_4_HI 0x2c
70 #define DSI_PKT_SEQ_5_LO 0x2d
71 #define DSI_PKT_SEQ_5_HI 0x2e
72 #define DSI_DCS_CMDS 0x33
73 #define DSI_PKT_LEN_0_1 0x34
74 #define DSI_PKT_LEN_2_3 0x35
75 #define DSI_PKT_LEN_4_5 0x36
76 #define DSI_PKT_LEN_6_7 0x37
77 #define DSI_PHY_TIMING_0 0x3c
78 #define DSI_PHY_TIMING_1 0x3d
79 #define DSI_PHY_TIMING_2 0x3e
80 #define DSI_BTA_TIMING 0x3f
81
82 #define DSI_TIMING_FIELD(value, period, hwinc) \
83 ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
84
85 #define DSI_TIMEOUT_0 0x44
86 #define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
87 #define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
88 #define DSI_TIMEOUT_1 0x45
89 #define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
90 #define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
91 #define DSI_TO_TALLY 0x46
92 #define DSI_TALLY_TA(x) (((x) & 0xff) << 16)
93 #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8)
94 #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0)
95 #define DSI_PAD_CONTROL_0 0x4b
96 #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
97 #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
98 #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
99 #define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
100 #define DSI_PAD_CONTROL_CD 0x4c
101 #define DSI_PAD_CD_STATUS 0x4d
102 #define DSI_VIDEO_MODE_CONTROL 0x4e
103 #define DSI_PAD_CONTROL_1 0x4f
104 #define DSI_PAD_CONTROL_2 0x50
105 #define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0)
106 #define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4)
107 #define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8)
108 #define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12)
109 #define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16)
110 #define DSI_PAD_CONTROL_3 0x51
111 #define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
112 #define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
113 #define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
114 #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
115 #define DSI_PAD_CONTROL_4 0x52
116 #define DSI_GANGED_MODE_CONTROL 0x53
117 #define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0)
118 #define DSI_GANGED_MODE_START 0x54
119 #define DSI_GANGED_MODE_SIZE 0x55
120 #define DSI_RAW_DATA_BYTE_COUNT 0x56
121 #define DSI_ULTRA_LOW_POWER_CONTROL 0x57
122 #define DSI_INIT_SEQ_DATA_8 0x58
123 #define DSI_INIT_SEQ_DATA_9 0x59
124 #define DSI_INIT_SEQ_DATA_10 0x5a
125 #define DSI_INIT_SEQ_DATA_11 0x5b
126 #define DSI_INIT_SEQ_DATA_12 0x5c
127 #define DSI_INIT_SEQ_DATA_13 0x5d
128 #define DSI_INIT_SEQ_DATA_14 0x5e
129 #define DSI_INIT_SEQ_DATA_15 0x5f
130
131 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
132 #define PKT_LEN0(len) (((len) & 0x07) << 0)
133 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
134 #define PKT_LEN1(len) (((len) & 0x07) << 10)
135 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
136 #define PKT_LEN2(len) (((len) & 0x07) << 20)
137
138 #define PKT_LP (1 << 30)
139 #define NUM_PKT_SEQ 12
140
141 #define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20)
142 #define DSIB_MODE_SHIFT 1
143 #define DSIB_MODE_CSI (0 << DSIB_MODE_SHIFT)
144 #define DSIB_MODE_DSI (1 << DSIB_MODE_SHIFT)
145
146 /*
147 * pixel format as used in the DSI_CONTROL_FORMAT field
148 */
149 enum tegra_dsi_format {
150 TEGRA_DSI_FORMAT_16P,
151 TEGRA_DSI_FORMAT_18NP,
152 TEGRA_DSI_FORMAT_18P,
153 TEGRA_DSI_FORMAT_24P,
154 };
155
156 enum dsi_dev {
157 DSI_A = 0,
158 DSI_B,
159 NUM_DSI,
160 };
161
162 struct panel_jdi;
163 struct tegra_mipi_device;
164 struct mipi_dsi_host;
165 struct mipi_dsi_msg;
166
167 #define MAX_DSI_VIDEO_FIFO_DEPTH 96
168 #define MAX_DSI_HOST_FIFO_DEPTH 64
169
170 struct tegra_dsi {
171 struct panel_jdi *panel;
172 //struct tegra_output output;
173 void *regs;
174 u8 channel;
175 unsigned long clk_rate;
176
177 unsigned long flags;
178 enum mipi_dsi_pixel_format format;
179 unsigned int lanes;
180
181 struct tegra_mipi_device *mipi;
182 struct mipi_dsi_host host;
183 bool enabled;
184
185 unsigned int video_fifo_depth;
186 unsigned int host_fifo_depth;
187
188 /* for ganged-mode support */
189 unsigned int ganged_lanes;
190 struct tegra_dsi *slave;
191 int ganged_mode;
192
193 struct tegra_dsi *master;
194 };
195
tegra_dsi_readl(struct tegra_dsi * dsi,unsigned long reg)196 static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
197 unsigned long reg)
198 {
199 return read32(dsi->regs + (reg << 2));
200 }
201
tegra_dsi_writel(struct tegra_dsi * dsi,unsigned long value,unsigned long reg)202 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
203 unsigned long reg)
204 {
205 write32(dsi->regs + (reg << 2), value);
206 }
207
208 #endif /* __TEGRA_DSI_H__ */
209