1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_APOLLOLAKE_PNPCONFIG_H_ 4 #define _SOC_APOLLOLAKE_PNPCONFIG_H_ 5 6 #include <soc/pcr_ids.h> 7 8 #define MAKE_MASK_INCLUSIVE(msb) MAKE_MASK(msb+1) 9 10 #define MAKE_MASK(msb) (uint32_t)((1ULL << (msb)) - 1) 11 12 #define MASK_VAL(msb, lsb, val) \ 13 ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb) 14 15 struct pnpconfig { 16 int msgport; 17 uint32_t msgregaddr; 18 uint32_t mask; 19 uint32_t value; 20 }; 21 22 #define AUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ 23 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID0 */ \ 24 { PID_AUNIT, 0x6430, MASK_VAL(7, 0, 0x1) }, \ 25 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID1 */ \ 26 { PID_AUNIT, 0x6430, MASK_VAL(15, 8, 0x1) }, \ 27 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID2 */ \ 28 { PID_AUNIT, 0x6430, MASK_VAL(23, 16, 0x0) }, \ 29 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID3 */ \ 30 { PID_AUNIT, 0x6430, MASK_VAL(31, 24, 0x1) }, \ 31 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID4 */ \ 32 { PID_AUNIT, 0x6434, MASK_VAL(7, 0, 0x0) }, \ 33 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID5 */ \ 34 { PID_AUNIT, 0x6434, MASK_VAL(15, 8, 0x1) }, \ 35 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID6 */ \ 36 { PID_AUNIT, 0x6434, MASK_VAL(23, 16, 0x1) }, \ 37 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID7 */ \ 38 { PID_AUNIT, 0x6434, MASK_VAL(31, 24, 0x1) }, \ 39 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID0 */ \ 40 { PID_AUNIT, 0x6438, MASK_VAL(7, 0, 0x1) }, \ 41 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID1 */ \ 42 { PID_AUNIT, 0x6438, MASK_VAL(15, 8, 0x1) }, \ 43 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID2 */ \ 44 { PID_AUNIT, 0x6438, MASK_VAL(23, 16, 0x1) }, \ 45 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID3 */ \ 46 { PID_AUNIT, 0x6438, MASK_VAL(31, 24, 0x1) }, \ 47 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID4 */ \ 48 { PID_AUNIT, 0x643c, MASK_VAL(7, 0, 0x1) }, \ 49 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID5 */ \ 50 { PID_AUNIT, 0x643c, MASK_VAL(15, 8, 0x1) }, \ 51 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID6 */ \ 52 { PID_AUNIT, 0x643c, MASK_VAL(23, 16, 0x1) }, \ 53 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID7 */ \ 54 { PID_AUNIT, 0x643c, MASK_VAL(31, 24, 0x1) }, \ 55 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID0 */ \ 56 { PID_AUNIT, 0x6440, MASK_VAL(7, 0, 0x1) }, \ 57 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID1 */ \ 58 { PID_AUNIT, 0x6440, MASK_VAL(15, 8, 0x1) }, \ 59 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID2 */ \ 60 { PID_AUNIT, 0x6440, MASK_VAL(23, 16, 0x0) }, \ 61 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID3 */ \ 62 { PID_AUNIT, 0x6440, MASK_VAL(31, 24, 0x0) }, \ 63 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.P */ \ 64 { PID_AUNIT, 0x6444, MASK_VAL(7, 0, 0x1) }, \ 65 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.NP */ \ 66 { PID_AUNIT, 0x6444, MASK_VAL(15, 8, 0x1) }, \ 67 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.C */ \ 68 { PID_AUNIT, 0x6444, MASK_VAL(23, 16, 0x1) }, \ 69 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID0 */ \ 70 { PID_AUNIT, 0x6448, MASK_VAL(7, 0, 0x8) }, \ 71 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID1 */ \ 72 { PID_AUNIT, 0x6448, MASK_VAL(15, 8, 0xff) }, \ 73 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID2 */ \ 74 { PID_AUNIT, 0x6448, MASK_VAL(23, 16, 0xff) }, \ 75 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID3 */ \ 76 { PID_AUNIT, 0x6448, MASK_VAL(31, 24, 0xff) }, \ 77 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID4 */ \ 78 { PID_AUNIT, 0x644c, MASK_VAL(7, 0, 0xff) }, \ 79 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID5 */ \ 80 { PID_AUNIT, 0x644c, MASK_VAL(15, 8, 0xff) }, \ 81 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID6 */ \ 82 { PID_AUNIT, 0x644c, MASK_VAL(23, 16, 0xff) }, \ 83 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID7 */ \ 84 { PID_AUNIT, 0x644c, MASK_VAL(31, 24, 0xff) }, \ 85 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_1_DISABLED */ \ 86 { PID_AUNIT, 0x6450, MASK_VAL(0, 0, 0x0) }, \ 87 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.HVM_MODE */ \ 88 { PID_AUNIT, 0x6450, MASK_VAL(1, 1, 0x0) }, \ 89 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.INTERLEAVE_MODE */ \ 90 { PID_AUNIT, 0x6450, MASK_VAL(3, 2, 0x2) }, \ 91 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_HASH_MASK */ \ 92 { PID_AUNIT, 0x6450, MASK_VAL(19, 6, 0x9) }, \ 93 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.CH_HASH_MASK */ \ 94 { PID_AUNIT, 0x6454, MASK_VAL(19, 6, 0x36) }, \ 95 /* A_CR_CHAP_SLCT1_MCHBAR.CHID_X_CNT_UPTXN */ \ 96 { PID_AUNIT, 0x6484, MASK_VAL(7, 0, 0xff) }, \ 97 /* A_CR_CHAP_SLCT1_MCHBAR.CHID_Y_CNT_UPTXN */ \ 98 { PID_AUNIT, 0x6484, MASK_VAL(23, 16, 0xff) } 99 100 #define AUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ 101 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID0 */ \ 102 { PID_AUNIT, 0x6430, MASK_VAL(7, 0, 0x1) }, \ 103 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID1 */ \ 104 { PID_AUNIT, 0x6430, MASK_VAL(15, 8, 0x1) }, \ 105 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID2 */ \ 106 { PID_AUNIT, 0x6430, MASK_VAL(23, 16, 0x0) }, \ 107 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID3 */ \ 108 { PID_AUNIT, 0x6430, MASK_VAL(31, 24, 0x1) }, \ 109 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID4 */ \ 110 { PID_AUNIT, 0x6434, MASK_VAL(7, 0, 0x0) }, \ 111 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID5 */ \ 112 { PID_AUNIT, 0x6434, MASK_VAL(15, 8, 0x1) }, \ 113 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID6 */ \ 114 { PID_AUNIT, 0x6434, MASK_VAL(23, 16, 0x1) }, \ 115 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID7 */ \ 116 { PID_AUNIT, 0x6434, MASK_VAL(31, 24, 0x1) }, \ 117 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID0 */ \ 118 { PID_AUNIT, 0x6438, MASK_VAL(7, 0, 0x1) }, \ 119 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID1 */ \ 120 { PID_AUNIT, 0x6438, MASK_VAL(15, 8, 0x1) }, \ 121 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID2 */ \ 122 { PID_AUNIT, 0x6438, MASK_VAL(23, 16, 0x1) }, \ 123 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID3 */ \ 124 { PID_AUNIT, 0x6438, MASK_VAL(31, 24, 0x1) }, \ 125 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID4 */ \ 126 { PID_AUNIT, 0x643c, MASK_VAL(7, 0, 0x1) }, \ 127 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID5 */ \ 128 { PID_AUNIT, 0x643c, MASK_VAL(15, 8, 0x1) }, \ 129 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID6 */ \ 130 { PID_AUNIT, 0x643c, MASK_VAL(23, 16, 0x1) }, \ 131 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID7 */ \ 132 { PID_AUNIT, 0x643c, MASK_VAL(31, 24, 0x1) }, \ 133 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID0 */ \ 134 { PID_AUNIT, 0x6440, MASK_VAL(7, 0, 0x1) }, \ 135 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID1 */ \ 136 { PID_AUNIT, 0x6440, MASK_VAL(15, 8, 0x1) }, \ 137 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID2 */ \ 138 { PID_AUNIT, 0x6440, MASK_VAL(23, 16, 0x0) }, \ 139 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID3 */ \ 140 { PID_AUNIT, 0x6440, MASK_VAL(31, 24, 0x0) }, \ 141 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.P */ \ 142 { PID_AUNIT, 0x6444, MASK_VAL(7, 0, 0x1) }, \ 143 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.NP */ \ 144 { PID_AUNIT, 0x6444, MASK_VAL(15, 8, 0x1) }, \ 145 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.C */ \ 146 { PID_AUNIT, 0x6444, MASK_VAL(23, 16, 0x1) }, \ 147 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID0 */ \ 148 { PID_AUNIT, 0x6448, MASK_VAL(7, 0, 0x8) }, \ 149 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID1 */ \ 150 { PID_AUNIT, 0x6448, MASK_VAL(15, 8, 0xff) }, \ 151 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID2 */ \ 152 { PID_AUNIT, 0x6448, MASK_VAL(23, 16, 0xff) }, \ 153 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID3 */ \ 154 { PID_AUNIT, 0x6448, MASK_VAL(31, 24, 0xff) }, \ 155 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID4 */ \ 156 { PID_AUNIT, 0x644c, MASK_VAL(7, 0, 0xff) }, \ 157 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID5 */ \ 158 { PID_AUNIT, 0x644c, MASK_VAL(15, 8, 0xff) }, \ 159 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID6 */ \ 160 { PID_AUNIT, 0x644c, MASK_VAL(23, 16, 0xff) }, \ 161 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID7 */ \ 162 { PID_AUNIT, 0x644c, MASK_VAL(31, 24, 0xff) }, \ 163 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_1_DISABLED */ \ 164 { PID_AUNIT, 0x6450, MASK_VAL(0, 0, 0x0) }, \ 165 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.HVM_MODE */ \ 166 { PID_AUNIT, 0x6450, MASK_VAL(1, 1, 0x0) }, \ 167 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.INTERLEAVE_MODE */ \ 168 { PID_AUNIT, 0x6450, MASK_VAL(3, 2, 0x2) }, \ 169 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_HASH_MASK */ \ 170 { PID_AUNIT, 0x6450, MASK_VAL(19, 6, 0x9) }, \ 171 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.CH_HASH_MASK */ \ 172 { PID_AUNIT, 0x6454, MASK_VAL(19, 6, 0x36) }, \ 173 /* A_CR_CHAP_SLCT1_MCHBAR.CHID_X_CNT_UPTXN */ \ 174 { PID_AUNIT, 0x6484, MASK_VAL(7, 0, 0xff) }, \ 175 /* A_CR_CHAP_SLCT1_MCHBAR.CHID_Y_CNT_UPTXN */ \ 176 { PID_AUNIT, 0x6484, MASK_VAL(23, 16, 0xff) } 177 178 #define AUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ 179 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID0 */ \ 180 { PID_AUNIT, 0x6430, MASK_VAL(7, 0, 0x1) }, \ 181 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID1 */ \ 182 { PID_AUNIT, 0x6430, MASK_VAL(15, 8, 0x1) }, \ 183 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID2 */ \ 184 { PID_AUNIT, 0x6430, MASK_VAL(23, 16, 0x0) }, \ 185 /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID3 */ \ 186 { PID_AUNIT, 0x6430, MASK_VAL(31, 24, 0x1) }, \ 187 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID4 */ \ 188 { PID_AUNIT, 0x6434, MASK_VAL(7, 0, 0x0) }, \ 189 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID5 */ \ 190 { PID_AUNIT, 0x6434, MASK_VAL(15, 8, 0x1) }, \ 191 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID6 */ \ 192 { PID_AUNIT, 0x6434, MASK_VAL(23, 16, 0x1) }, \ 193 /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID7 */ \ 194 { PID_AUNIT, 0x6434, MASK_VAL(31, 24, 0x1) }, \ 195 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID0 */ \ 196 { PID_AUNIT, 0x6438, MASK_VAL(7, 0, 0x1) }, \ 197 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID1 */ \ 198 { PID_AUNIT, 0x6438, MASK_VAL(15, 8, 0x1) }, \ 199 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID2 */ \ 200 { PID_AUNIT, 0x6438, MASK_VAL(23, 16, 0x1) }, \ 201 /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID3 */ \ 202 { PID_AUNIT, 0x6438, MASK_VAL(31, 24, 0x1) }, \ 203 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID4 */ \ 204 { PID_AUNIT, 0x643c, MASK_VAL(7, 0, 0x1) }, \ 205 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID5 */ \ 206 { PID_AUNIT, 0x643c, MASK_VAL(15, 8, 0x1) }, \ 207 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID6 */ \ 208 { PID_AUNIT, 0x643c, MASK_VAL(23, 16, 0x1) }, \ 209 /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID7 */ \ 210 { PID_AUNIT, 0x643c, MASK_VAL(31, 24, 0x1) }, \ 211 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID0 */ \ 212 { PID_AUNIT, 0x6440, MASK_VAL(7, 0, 0x1) }, \ 213 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID1 */ \ 214 { PID_AUNIT, 0x6440, MASK_VAL(15, 8, 0x1) }, \ 215 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID2 */ \ 216 { PID_AUNIT, 0x6440, MASK_VAL(23, 16, 0x0) }, \ 217 /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID3 */ \ 218 { PID_AUNIT, 0x6440, MASK_VAL(31, 24, 0x0) }, \ 219 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.P */ \ 220 { PID_AUNIT, 0x6444, MASK_VAL(7, 0, 0x1) }, \ 221 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.NP */ \ 222 { PID_AUNIT, 0x6444, MASK_VAL(15, 8, 0x1) }, \ 223 /* A_CR_CRDARB_GCNT_CLS_MCHBAR.C */ \ 224 { PID_AUNIT, 0x6444, MASK_VAL(23, 16, 0x1) }, \ 225 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID0 */ \ 226 { PID_AUNIT, 0x6448, MASK_VAL(7, 0, 0x8) }, \ 227 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID1 */ \ 228 { PID_AUNIT, 0x6448, MASK_VAL(15, 8, 0xff) }, \ 229 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID2 */ \ 230 { PID_AUNIT, 0x6448, MASK_VAL(23, 16, 0xff) }, \ 231 /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID3 */ \ 232 { PID_AUNIT, 0x6448, MASK_VAL(31, 24, 0xff) }, \ 233 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID4 */ \ 234 { PID_AUNIT, 0x644c, MASK_VAL(7, 0, 0xff) }, \ 235 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID5 */ \ 236 { PID_AUNIT, 0x644c, MASK_VAL(15, 8, 0xff) }, \ 237 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID6 */ \ 238 { PID_AUNIT, 0x644c, MASK_VAL(23, 16, 0xff) }, \ 239 /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID7 */ \ 240 { PID_AUNIT, 0x644c, MASK_VAL(31, 24, 0xff) }, \ 241 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_1_DISABLED */ \ 242 { PID_AUNIT, 0x6450, MASK_VAL(0, 0, 0x0) }, \ 243 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.HVM_MODE */ \ 244 { PID_AUNIT, 0x6450, MASK_VAL(1, 1, 0x0) }, \ 245 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.INTERLEAVE_MODE */ \ 246 { PID_AUNIT, 0x6450, MASK_VAL(3, 2, 0x2) }, \ 247 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_HASH_MASK */ \ 248 { PID_AUNIT, 0x6450, MASK_VAL(19, 6, 0x9) }, \ 249 /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.CH_HASH_MASK */ \ 250 { PID_AUNIT, 0x6454, MASK_VAL(19, 6, 0x36) }, \ 251 /* A_CR_CHAP_SLCT1_MCHBAR.CHID_X_CNT_UPTXN */ \ 252 { PID_AUNIT, 0x6484, MASK_VAL(7, 0, 0xff) }, \ 253 /* A_CR_CHAP_SLCT1_MCHBAR.CHID_Y_CNT_UPTXN */ \ 254 { PID_AUNIT, 0x6484, MASK_VAL(23, 16, 0xff) } 255 256 #define BUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ 257 /* B_CR_BARBCTRL0.AGENT0_WEIGHT */ \ 258 { PID_BUNIT, 0x6d4c, MASK_VAL(5, 0, 0x8) }, \ 259 /* B_CR_BARBCTRL0.AGENT1_WEIGHT */ \ 260 { PID_BUNIT, 0x6d4c, MASK_VAL(13, 8, 0x8) }, \ 261 /* B_CR_BARBCTRL0.AGENT2_WEIGHT */ \ 262 { PID_BUNIT, 0x6d4c, MASK_VAL(21, 16, 0x8) }, \ 263 /* B_CR_BARBCTRL0.AGENT3_WEIGHT */ \ 264 { PID_BUNIT, 0x6d4c, MASK_VAL(29, 24, 0x8) }, \ 265 /* B_CR_BARBCTRL1.AGENT4_WEIGHT */ \ 266 { PID_BUNIT, 0x6d50, MASK_VAL(5, 0, 0x8) }, \ 267 /* B_CR_BARBCTRL1.AGENT5_WEIGHT */ \ 268 { PID_BUNIT, 0x6d50, MASK_VAL(13, 8, 0x8) }, \ 269 /* B_CR_BARBCTRL1.AGENT6_WEIGHT */ \ 270 { PID_BUNIT, 0x6d50, MASK_VAL(21, 16, 0x8) }, \ 271 /* B_CR_BARBCTRL1.AGENT7_WEIGHT */ \ 272 { PID_BUNIT, 0x6d50, MASK_VAL(29, 24, 0x8) }, \ 273 /* B_CR_BSCHWT0.AGENT0_WEIGHT */ \ 274 { PID_BUNIT, 0x6d54, MASK_VAL(5, 0, 0x8) }, \ 275 /* B_CR_BSCHWT0.AGENT1_WEIGHT */ \ 276 { PID_BUNIT, 0x6d54, MASK_VAL(13, 8, 0x8) }, \ 277 /* B_CR_BSCHWT0.AGENT2_WEIGHT */ \ 278 { PID_BUNIT, 0x6d54, MASK_VAL(21, 16, 0x8) }, \ 279 /* B_CR_BSCHWT0.AGENT3_WEIGHT */ \ 280 { PID_BUNIT, 0x6d54, MASK_VAL(29, 24, 0x8) }, \ 281 /* B_CR_BSCHWT1.AGENT4_WEIGHT */ \ 282 { PID_BUNIT, 0x6d58, MASK_VAL(5, 0, 0x8) }, \ 283 /* B_CR_BSCHWT1.AGENT5_WEIGHT */ \ 284 { PID_BUNIT, 0x6d58, MASK_VAL(13, 8, 0x8) }, \ 285 /* B_CR_BSCHWT1.AGENT6_WEIGHT */ \ 286 { PID_BUNIT, 0x6d58, MASK_VAL(21, 16, 0x8) }, \ 287 /* B_CR_BSCHWT1.AGENT7_WEIGHT */ \ 288 { PID_BUNIT, 0x6d58, MASK_VAL(29, 24, 0x8) }, \ 289 /* B_CR_BSCHWT2.AGENT8_WEIGHT */ \ 290 { PID_BUNIT, 0x6d5c, MASK_VAL(5, 0, 0x8) }, \ 291 /* B_CR_BSCHWT2.AGENT9_WEIGHT */ \ 292 { PID_BUNIT, 0x6d5c, MASK_VAL(13, 8, 0x8) }, \ 293 /* B_CR_BSCHWT2.AGENT10_WEIGHT */ \ 294 { PID_BUNIT, 0x6d5c, MASK_VAL(21, 16, 0x8) }, \ 295 /* B_CR_BSCHWT2.AGENT11_WEIGHT */ \ 296 { PID_BUNIT, 0x6d5c, MASK_VAL(29, 24, 0x8) }, \ 297 /* B_CR_BSCHWT3.AGENT12_WEIGHT */ \ 298 { PID_BUNIT, 0x6d60, MASK_VAL(5, 0, 0x8) }, \ 299 /* B_CR_BSCHWT3.AGENT13_WEIGHT */ \ 300 { PID_BUNIT, 0x6d60, MASK_VAL(13, 8, 0x8) }, \ 301 /* B_CR_BSCHWT3.AGENT14_WEIGHT */ \ 302 { PID_BUNIT, 0x6d60, MASK_VAL(21, 16, 0x8) }, \ 303 /* B_CR_BSCHWT3.AGENT15_WEIGHT */ \ 304 { PID_BUNIT, 0x6d60, MASK_VAL(29, 24, 0x8) }, \ 305 /* B_CR_BWFLUSH.DIRTY_HWM */ \ 306 { PID_BUNIT, 0x6d64, MASK_VAL(7, 0, 0x1b) }, \ 307 /* B_CR_BWFLUSH.DIRTY_LWM */ \ 308 { PID_BUNIT, 0x6d64, MASK_VAL(15, 8, 0x0) }, \ 309 /* B_CR_BWFLUSH.FLUSH_THRESHOLD */ \ 310 { PID_BUNIT, 0x6d64, MASK_VAL(31, 24, 0x27) }, \ 311 /* B_CR_BFLWT.READ_WEIGHTS */ \ 312 { PID_BUNIT, 0x6d68, MASK_VAL(5, 0, 0x1) }, \ 313 /* B_CR_BFLWT.WRITE_WEIGHTS */ \ 314 { PID_BUNIT, 0x6d68, MASK_VAL(13, 8, 0x1) }, \ 315 /* B_CR_BFLWT.DISABLE_FLUSH_WEIGHTS */ \ 316 { PID_BUNIT, 0x6d68, MASK_VAL(31, 31, 0x0) }, \ 317 /* B_CR_BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \ 318 { PID_BUNIT, 0x6d6c, MASK_VAL(5, 0, 0xf) }, \ 319 /* B_CR_BISOCWT.ISOC_REQUEST_WEIGHTS */ \ 320 { PID_BUNIT, 0x6d6c, MASK_VAL(13, 8, 0x3f) }, \ 321 /* B_CR_BISOCWT.ENABLE_ISOC_WEIGHTS */ \ 322 { PID_BUNIT, 0x6d6c, MASK_VAL(31, 31, 0x1) }, \ 323 /* B_CR_BCTRL2.DIRTY_STALL */ \ 324 { PID_BUNIT, 0x6d70, MASK_VAL(0, 0, 0x0) } 325 326 #define BUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ 327 /* B_CR_BARBCTRL0.AGENT0_WEIGHT */ \ 328 { PID_BUNIT, 0x6d4c, MASK_VAL(5, 0, 0x4) }, \ 329 /* B_CR_BARBCTRL0.AGENT1_WEIGHT */ \ 330 { PID_BUNIT, 0x6d4c, MASK_VAL(13, 8, 0x4) }, \ 331 /* B_CR_BARBCTRL0.AGENT2_WEIGHT */ \ 332 { PID_BUNIT, 0x6d4c, MASK_VAL(21, 16, 0x4) }, \ 333 /* B_CR_BARBCTRL0.AGENT3_WEIGHT */ \ 334 { PID_BUNIT, 0x6d4c, MASK_VAL(29, 24, 0x4) }, \ 335 /* B_CR_BARBCTRL1.AGENT4_WEIGHT */ \ 336 { PID_BUNIT, 0x6d50, MASK_VAL(5, 0, 0x4) }, \ 337 /* B_CR_BARBCTRL1.AGENT5_WEIGHT */ \ 338 { PID_BUNIT, 0x6d50, MASK_VAL(13, 8, 0x4) }, \ 339 /* B_CR_BARBCTRL1.AGENT6_WEIGHT */ \ 340 { PID_BUNIT, 0x6d50, MASK_VAL(21, 16, 0x4) }, \ 341 /* B_CR_BARBCTRL1.AGENT7_WEIGHT */ \ 342 { PID_BUNIT, 0x6d50, MASK_VAL(29, 24, 0x4) }, \ 343 /* B_CR_BSCHWT0.AGENT0_WEIGHT */ \ 344 { PID_BUNIT, 0x6d54, MASK_VAL(5, 0, 0x4) }, \ 345 /* B_CR_BSCHWT0.AGENT1_WEIGHT */ \ 346 { PID_BUNIT, 0x6d54, MASK_VAL(13, 8, 0x4) }, \ 347 /* B_CR_BSCHWT0.AGENT2_WEIGHT */ \ 348 { PID_BUNIT, 0x6d54, MASK_VAL(21, 16, 0x4) }, \ 349 /* B_CR_BSCHWT0.AGENT3_WEIGHT */ \ 350 { PID_BUNIT, 0x6d54, MASK_VAL(29, 24, 0x4) }, \ 351 /* B_CR_BSCHWT1.AGENT4_WEIGHT */ \ 352 { PID_BUNIT, 0x6d58, MASK_VAL(5, 0, 0x4) }, \ 353 /* B_CR_BSCHWT1.AGENT5_WEIGHT */ \ 354 { PID_BUNIT, 0x6d58, MASK_VAL(13, 8, 0x4) }, \ 355 /* B_CR_BSCHWT1.AGENT6_WEIGHT */ \ 356 { PID_BUNIT, 0x6d58, MASK_VAL(21, 16, 0x4) }, \ 357 /* B_CR_BSCHWT1.AGENT7_WEIGHT */ \ 358 { PID_BUNIT, 0x6d58, MASK_VAL(29, 24, 0x4) }, \ 359 /* B_CR_BSCHWT2.AGENT8_WEIGHT */ \ 360 { PID_BUNIT, 0x6d5c, MASK_VAL(5, 0, 0x4) }, \ 361 /* B_CR_BSCHWT2.AGENT9_WEIGHT */ \ 362 { PID_BUNIT, 0x6d5c, MASK_VAL(13, 8, 0x4) }, \ 363 /* B_CR_BSCHWT2.AGENT10_WEIGHT */ \ 364 { PID_BUNIT, 0x6d5c, MASK_VAL(21, 16, 0x4) }, \ 365 /* B_CR_BSCHWT2.AGENT11_WEIGHT */ \ 366 { PID_BUNIT, 0x6d5c, MASK_VAL(29, 24, 0x4) }, \ 367 /* B_CR_BSCHWT3.AGENT12_WEIGHT */ \ 368 { PID_BUNIT, 0x6d60, MASK_VAL(5, 0, 0x4) }, \ 369 /* B_CR_BSCHWT3.AGENT13_WEIGHT */ \ 370 { PID_BUNIT, 0x6d60, MASK_VAL(13, 8, 0x4) }, \ 371 /* B_CR_BSCHWT3.AGENT14_WEIGHT */ \ 372 { PID_BUNIT, 0x6d60, MASK_VAL(21, 16, 0x4) }, \ 373 /* B_CR_BSCHWT3.AGENT15_WEIGHT */ \ 374 { PID_BUNIT, 0x6d60, MASK_VAL(29, 24, 0x4) }, \ 375 /* B_CR_BWFLUSH.DIRTY_HWM */ \ 376 { PID_BUNIT, 0x6d64, MASK_VAL(7, 0, 0x0) }, \ 377 /* B_CR_BWFLUSH.DIRTY_LWM */ \ 378 { PID_BUNIT, 0x6d64, MASK_VAL(15, 8, 0x0) }, \ 379 /* B_CR_BWFLUSH.FLUSH_THRESHOLD */ \ 380 { PID_BUNIT, 0x6d64, MASK_VAL(31, 24, 0x0) }, \ 381 /* B_CR_BFLWT.READ_WEIGHTS */ \ 382 { PID_BUNIT, 0x6d68, MASK_VAL(5, 0, 0x0) }, \ 383 /* B_CR_BFLWT.WRITE_WEIGHTS */ \ 384 { PID_BUNIT, 0x6d68, MASK_VAL(13, 8, 0x0) }, \ 385 /* B_CR_BFLWT.DISABLE_FLUSH_WEIGHTS */ \ 386 { PID_BUNIT, 0x6d68, MASK_VAL(31, 31, 0x0) }, \ 387 /* B_CR_BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \ 388 { PID_BUNIT, 0x6d6c, MASK_VAL(5, 0, 0x0) }, \ 389 /* B_CR_BISOCWT.ISOC_REQUEST_WEIGHTS */ \ 390 { PID_BUNIT, 0x6d6c, MASK_VAL(13, 8, 0x0) }, \ 391 /* B_CR_BISOCWT.ENABLE_ISOC_WEIGHTS */ \ 392 { PID_BUNIT, 0x6d6c, MASK_VAL(31, 31, 0x0) }, \ 393 /* B_CR_BCTRL2.DIRTY_STALL */ \ 394 { PID_BUNIT, 0x6d70, MASK_VAL(0, 0, 0x0) } 395 396 #define BUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ 397 /* B_CR_BARBCTRL0.AGENT0_WEIGHT */ \ 398 { PID_BUNIT, 0x6d4c, MASK_VAL(5, 0, 0x4) }, \ 399 /* B_CR_BARBCTRL0.AGENT1_WEIGHT */ \ 400 { PID_BUNIT, 0x6d4c, MASK_VAL(13, 8, 0x4) }, \ 401 /* B_CR_BARBCTRL0.AGENT2_WEIGHT */ \ 402 { PID_BUNIT, 0x6d4c, MASK_VAL(21, 16, 0x4) }, \ 403 /* B_CR_BARBCTRL0.AGENT3_WEIGHT */ \ 404 { PID_BUNIT, 0x6d4c, MASK_VAL(29, 24, 0x4) }, \ 405 /* B_CR_BARBCTRL1.AGENT4_WEIGHT */ \ 406 { PID_BUNIT, 0x6d50, MASK_VAL(5, 0, 0x4) }, \ 407 /* B_CR_BARBCTRL1.AGENT5_WEIGHT */ \ 408 { PID_BUNIT, 0x6d50, MASK_VAL(13, 8, 0x4) }, \ 409 /* B_CR_BARBCTRL1.AGENT6_WEIGHT */ \ 410 { PID_BUNIT, 0x6d50, MASK_VAL(21, 16, 0x4) }, \ 411 /* B_CR_BARBCTRL1.AGENT7_WEIGHT */ \ 412 { PID_BUNIT, 0x6d50, MASK_VAL(29, 24, 0x4) }, \ 413 /* B_CR_BSCHWT0.AGENT0_WEIGHT */ \ 414 { PID_BUNIT, 0x6d54, MASK_VAL(5, 0, 0x4) }, \ 415 /* B_CR_BSCHWT0.AGENT1_WEIGHT */ \ 416 { PID_BUNIT, 0x6d54, MASK_VAL(13, 8, 0x4) }, \ 417 /* B_CR_BSCHWT0.AGENT2_WEIGHT */ \ 418 { PID_BUNIT, 0x6d54, MASK_VAL(21, 16, 0x4) }, \ 419 /* B_CR_BSCHWT0.AGENT3_WEIGHT */ \ 420 { PID_BUNIT, 0x6d54, MASK_VAL(29, 24, 0x4) }, \ 421 /* B_CR_BSCHWT1.AGENT4_WEIGHT */ \ 422 { PID_BUNIT, 0x6d58, MASK_VAL(5, 0, 0x4) }, \ 423 /* B_CR_BSCHWT1.AGENT5_WEIGHT */ \ 424 { PID_BUNIT, 0x6d58, MASK_VAL(13, 8, 0x4) }, \ 425 /* B_CR_BSCHWT1.AGENT6_WEIGHT */ \ 426 { PID_BUNIT, 0x6d58, MASK_VAL(21, 16, 0x4) }, \ 427 /* B_CR_BSCHWT1.AGENT7_WEIGHT */ \ 428 { PID_BUNIT, 0x6d58, MASK_VAL(29, 24, 0x4) }, \ 429 /* B_CR_BSCHWT2.AGENT8_WEIGHT */ \ 430 { PID_BUNIT, 0x6d5c, MASK_VAL(5, 0, 0x4) }, \ 431 /* B_CR_BSCHWT2.AGENT9_WEIGHT */ \ 432 { PID_BUNIT, 0x6d5c, MASK_VAL(13, 8, 0x4) }, \ 433 /* B_CR_BSCHWT2.AGENT10_WEIGHT */ \ 434 { PID_BUNIT, 0x6d5c, MASK_VAL(21, 16, 0x4) }, \ 435 /* B_CR_BSCHWT2.AGENT11_WEIGHT */ \ 436 { PID_BUNIT, 0x6d5c, MASK_VAL(29, 24, 0x4) }, \ 437 /* B_CR_BSCHWT3.AGENT12_WEIGHT */ \ 438 { PID_BUNIT, 0x6d60, MASK_VAL(5, 0, 0x4) }, \ 439 /* B_CR_BSCHWT3.AGENT13_WEIGHT */ \ 440 { PID_BUNIT, 0x6d60, MASK_VAL(13, 8, 0x4) }, \ 441 /* B_CR_BSCHWT3.AGENT14_WEIGHT */ \ 442 { PID_BUNIT, 0x6d60, MASK_VAL(21, 16, 0x4) }, \ 443 /* B_CR_BSCHWT3.AGENT15_WEIGHT */ \ 444 { PID_BUNIT, 0x6d60, MASK_VAL(29, 24, 0x4) }, \ 445 /* B_CR_BWFLUSH.DIRTY_HWM */ \ 446 { PID_BUNIT, 0x6d64, MASK_VAL(7, 0, 0x0) }, \ 447 /* B_CR_BWFLUSH.DIRTY_LWM */ \ 448 { PID_BUNIT, 0x6d64, MASK_VAL(15, 8, 0x0) }, \ 449 /* B_CR_BWFLUSH.FLUSH_THRESHOLD */ \ 450 { PID_BUNIT, 0x6d64, MASK_VAL(31, 24, 0x0) }, \ 451 /* B_CR_BFLWT.READ_WEIGHTS */ \ 452 { PID_BUNIT, 0x6d68, MASK_VAL(5, 0, 0x0) }, \ 453 /* B_CR_BFLWT.WRITE_WEIGHTS */ \ 454 { PID_BUNIT, 0x6d68, MASK_VAL(13, 8, 0x0) }, \ 455 /* B_CR_BFLWT.DISABLE_FLUSH_WEIGHTS */ \ 456 { PID_BUNIT, 0x6d68, MASK_VAL(31, 31, 0x0) }, \ 457 /* B_CR_BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \ 458 { PID_BUNIT, 0x6d6c, MASK_VAL(5, 0, 0x0) }, \ 459 /* B_CR_BISOCWT.ISOC_REQUEST_WEIGHTS */ \ 460 { PID_BUNIT, 0x6d6c, MASK_VAL(13, 8, 0x0) }, \ 461 /* B_CR_BISOCWT.ENABLE_ISOC_WEIGHTS */ \ 462 { PID_BUNIT, 0x6d6c, MASK_VAL(31, 31, 0x0) }, \ 463 /* B_CR_BCTRL2.DIRTY_STALL */ \ 464 { PID_BUNIT, 0x6d70, MASK_VAL(0, 0, 0x0) } 465 466 #define TUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ 467 /* CTL_MCHBAR.ALWAYS_SNP_PII2 */ \ 468 { PID_TUNIT, 0x7810, MASK_VAL(0, 0, 0x0) }, \ 469 /* CTL_MCHBAR.OUTSTND_SNP */ \ 470 { PID_TUNIT, 0x7810, MASK_VAL(1, 1, 0x0) }, \ 471 /* CTL_MCHBAR.DIS_LIVE_BRAM_BYP_IDI */ \ 472 { PID_TUNIT, 0x7810, MASK_VAL(2, 2, 0x0) }, \ 473 /* CTL_MCHBAR.ALWAYS_SNP_IDI */ \ 474 { PID_TUNIT, 0x7810, MASK_VAL(3, 3, 0x0) }, \ 475 /* CTL_MCHBAR.SNPINV */ \ 476 { PID_TUNIT, 0x7810, MASK_VAL(7, 7, 0x0) }, \ 477 /* CTL_MCHBAR.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ 478 { PID_TUNIT, 0x7810, MASK_VAL(18, 18, 0x0) }, \ 479 /* CTL_MCHBAR.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ 480 { PID_TUNIT, 0x7810, MASK_VAL(19, 19, 0x0) }, \ 481 /* CTL_MCHBAR.DISABLE_SNOOPING_GT */ \ 482 { PID_TUNIT, 0x7810, MASK_VAL(20, 20, 0x0) }, \ 483 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ 484 { PID_TUNIT, 0x781c, MASK_VAL(0, 0, 0x1) }, \ 485 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ 486 { PID_TUNIT, 0x781c, MASK_VAL(1, 1, 0x1) }, \ 487 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ 488 { PID_TUNIT, 0x781c, MASK_VAL(2, 2, 0x0) }, \ 489 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ 490 { PID_TUNIT, 0x781c, MASK_VAL(3, 3, 0x0) }, \ 491 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ 492 { PID_TUNIT, 0x781c, MASK_VAL(4, 4, 0x0) }, \ 493 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ 494 { PID_TUNIT, 0x781c, MASK_VAL(5, 5, 0x1) }, \ 495 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ 496 { PID_TUNIT, 0x781c, MASK_VAL(6, 6, 0x1) }, \ 497 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ 498 { PID_TUNIT, 0x781c, MASK_VAL(7, 7, 0x1) }, \ 499 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ 500 { PID_TUNIT, 0x7820, MASK_VAL(0, 0, 0x1) }, \ 501 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ 502 { PID_TUNIT, 0x7820, MASK_VAL(1, 1, 0x1) }, \ 503 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ 504 { PID_TUNIT, 0x7820, MASK_VAL(2, 2, 0x0) }, \ 505 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ 506 { PID_TUNIT, 0x7820, MASK_VAL(3, 3, 0x0) }, \ 507 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ 508 { PID_TUNIT, 0x7820, MASK_VAL(4, 4, 0x1) }, \ 509 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ 510 { PID_TUNIT, 0x7820, MASK_VAL(5, 5, 0x1) }, \ 511 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ 512 { PID_TUNIT, 0x7820, MASK_VAL(6, 6, 0x1) }, \ 513 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ 514 { PID_TUNIT, 0x7820, MASK_VAL(7, 7, 0x1) }, \ 515 /* T_CR_CTL.ALWAYS_SNP_PII2 */ \ 516 { PID_TUNIT, 0x523c, MASK_VAL(0, 0, 0x0) }, \ 517 /* T_CR_CTL.DIS_LIVE_BRAM_BYP_IDI */ \ 518 { PID_TUNIT, 0x523c, MASK_VAL(2, 2, 0x0) }, \ 519 /* T_CR_CTL.ALWAYS_SNP_IDI */ \ 520 { PID_TUNIT, 0x523c, MASK_VAL(3, 3, 0x0) }, \ 521 /* T_CR_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ 522 { PID_TUNIT, 0x523c, MASK_VAL(18, 18, 0x0) }, \ 523 /* T_CR_CTL.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ 524 { PID_TUNIT, 0x523c, MASK_VAL(19, 19, 0x0) }, \ 525 /* T_CR_CTL.DISABLE_SNOOPING_GT */ \ 526 { PID_TUNIT, 0x523c, MASK_VAL(20, 20, 0x0) }, \ 527 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ 528 { PID_TUNIT, 0x5288, MASK_VAL(0, 0, 0x1) }, \ 529 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ 530 { PID_TUNIT, 0x5288, MASK_VAL(1, 1, 0x1) }, \ 531 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ 532 { PID_TUNIT, 0x5288, MASK_VAL(2, 2, 0x0) }, \ 533 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ 534 { PID_TUNIT, 0x5288, MASK_VAL(3, 3, 0x0) }, \ 535 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ 536 { PID_TUNIT, 0x5288, MASK_VAL(4, 4, 0x1) }, \ 537 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ 538 { PID_TUNIT, 0x5288, MASK_VAL(5, 5, 0x1) }, \ 539 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ 540 { PID_TUNIT, 0x5288, MASK_VAL(6, 6, 0x1) }, \ 541 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ 542 { PID_TUNIT, 0x5288, MASK_VAL(7, 7, 0x1) }, \ 543 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ 544 { PID_TUNIT, 0x528c, MASK_VAL(0, 0, 0x1) }, \ 545 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ 546 { PID_TUNIT, 0x528c, MASK_VAL(1, 1, 0x1) }, \ 547 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ 548 { PID_TUNIT, 0x528c, MASK_VAL(2, 2, 0x0) }, \ 549 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ 550 { PID_TUNIT, 0x528c, MASK_VAL(3, 3, 0x0) }, \ 551 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ 552 { PID_TUNIT, 0x528c, MASK_VAL(4, 4, 0x1) }, \ 553 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ 554 { PID_TUNIT, 0x528c, MASK_VAL(5, 5, 0x1) }, \ 555 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ 556 { PID_TUNIT, 0x528c, MASK_VAL(6, 6, 0x1) }, \ 557 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ 558 { PID_TUNIT, 0x528c, MASK_VAL(7, 7, 0x1) } 559 560 #define TUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ 561 /* CTL_MCHBAR.ALWAYS_SNP_PII2 */ \ 562 { PID_TUNIT, 0x7810, MASK_VAL(0, 0, 0x0) }, \ 563 /* CTL_MCHBAR.OUTSTND_SNP */ \ 564 { PID_TUNIT, 0x7810, MASK_VAL(1, 1, 0x0) }, \ 565 /* CTL_MCHBAR.DIS_LIVE_BRAM_BYP_IDI */ \ 566 { PID_TUNIT, 0x7810, MASK_VAL(2, 2, 0x0) }, \ 567 /* CTL_MCHBAR.ALWAYS_SNP_IDI */ \ 568 { PID_TUNIT, 0x7810, MASK_VAL(3, 3, 0x0) }, \ 569 /* CTL_MCHBAR.SNPINV */ \ 570 { PID_TUNIT, 0x7810, MASK_VAL(7, 7, 0x0) }, \ 571 /* CTL_MCHBAR.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ 572 { PID_TUNIT, 0x7810, MASK_VAL(18, 18, 0x0) }, \ 573 /* CTL_MCHBAR.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ 574 { PID_TUNIT, 0x7810, MASK_VAL(19, 19, 0x0) }, \ 575 /* CTL_MCHBAR.DISABLE_SNOOPING_GT */ \ 576 { PID_TUNIT, 0x7810, MASK_VAL(20, 20, 0x0) }, \ 577 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ 578 { PID_TUNIT, 0x781c, MASK_VAL(0, 0, 0x1) }, \ 579 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ 580 { PID_TUNIT, 0x781c, MASK_VAL(1, 1, 0x1) }, \ 581 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ 582 { PID_TUNIT, 0x781c, MASK_VAL(2, 2, 0x0) }, \ 583 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ 584 { PID_TUNIT, 0x781c, MASK_VAL(3, 3, 0x0) }, \ 585 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ 586 { PID_TUNIT, 0x781c, MASK_VAL(4, 4, 0x1) }, \ 587 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ 588 { PID_TUNIT, 0x781c, MASK_VAL(5, 5, 0x1) }, \ 589 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ 590 { PID_TUNIT, 0x781c, MASK_VAL(6, 6, 0x1) }, \ 591 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ 592 { PID_TUNIT, 0x781c, MASK_VAL(7, 7, 0x1) }, \ 593 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ 594 { PID_TUNIT, 0x7820, MASK_VAL(0, 0, 0x1) }, \ 595 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ 596 { PID_TUNIT, 0x7820, MASK_VAL(1, 1, 0x1) }, \ 597 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ 598 { PID_TUNIT, 0x7820, MASK_VAL(2, 2, 0x0) }, \ 599 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ 600 { PID_TUNIT, 0x7820, MASK_VAL(3, 3, 0x0) }, \ 601 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ 602 { PID_TUNIT, 0x7820, MASK_VAL(4, 4, 0x1) }, \ 603 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ 604 { PID_TUNIT, 0x7820, MASK_VAL(5, 5, 0x1) }, \ 605 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ 606 { PID_TUNIT, 0x7820, MASK_VAL(6, 6, 0x1) }, \ 607 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ 608 { PID_TUNIT, 0x7820, MASK_VAL(7, 7, 0x1) }, \ 609 /* T_CR_CTL.ALWAYS_SNP_PII2 */ \ 610 { PID_TUNIT, 0x523c, MASK_VAL(0, 0, 0x0) }, \ 611 /* T_CR_CTL.DIS_LIVE_BRAM_BYP_IDI */ \ 612 { PID_TUNIT, 0x523c, MASK_VAL(2, 2, 0x0) }, \ 613 /* T_CR_CTL.ALWAYS_SNP_IDI */ \ 614 { PID_TUNIT, 0x523c, MASK_VAL(3, 3, 0x0) }, \ 615 /* T_CR_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ 616 { PID_TUNIT, 0x523c, MASK_VAL(18, 18, 0x0) }, \ 617 /* T_CR_CTL.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ 618 { PID_TUNIT, 0x523c, MASK_VAL(19, 19, 0x0) }, \ 619 /* T_CR_CTL.DISABLE_SNOOPING_GT */ \ 620 { PID_TUNIT, 0x523c, MASK_VAL(20, 20, 0x0) }, \ 621 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ 622 { PID_TUNIT, 0x5288, MASK_VAL(0, 0, 0x1) }, \ 623 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ 624 { PID_TUNIT, 0x5288, MASK_VAL(1, 1, 0x1) }, \ 625 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ 626 { PID_TUNIT, 0x5288, MASK_VAL(2, 2, 0x0) }, \ 627 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ 628 { PID_TUNIT, 0x5288, MASK_VAL(3, 3, 0x0) }, \ 629 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ 630 { PID_TUNIT, 0x5288, MASK_VAL(4, 4, 0x1) }, \ 631 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ 632 { PID_TUNIT, 0x5288, MASK_VAL(5, 5, 0x1) }, \ 633 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ 634 { PID_TUNIT, 0x5288, MASK_VAL(6, 6, 0x1) }, \ 635 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ 636 { PID_TUNIT, 0x5288, MASK_VAL(7, 7, 0x1) }, \ 637 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ 638 { PID_TUNIT, 0x528c, MASK_VAL(0, 0, 0x1) }, \ 639 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ 640 { PID_TUNIT, 0x528c, MASK_VAL(1, 1, 0x1) }, \ 641 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ 642 { PID_TUNIT, 0x528c, MASK_VAL(2, 2, 0x0) }, \ 643 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ 644 { PID_TUNIT, 0x528c, MASK_VAL(3, 3, 0x0) }, \ 645 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ 646 { PID_TUNIT, 0x528c, MASK_VAL(4, 4, 0x1) }, \ 647 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ 648 { PID_TUNIT, 0x528c, MASK_VAL(5, 5, 0x1) }, \ 649 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ 650 { PID_TUNIT, 0x528c, MASK_VAL(6, 6, 0x1) }, \ 651 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ 652 { PID_TUNIT, 0x528c, MASK_VAL(7, 7, 0x1) } 653 654 #define TUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ 655 /* CTL_MCHBAR.ALWAYS_SNP_PII2 */ \ 656 { PID_TUNIT, 0x7810, MASK_VAL(0, 0, 0x0) }, \ 657 /* CTL_MCHBAR.OUTSTND_SNP */ \ 658 { PID_TUNIT, 0x7810, MASK_VAL(1, 1, 0x0) }, \ 659 /* CTL_MCHBAR.DIS_LIVE_BRAM_BYP_IDI */ \ 660 { PID_TUNIT, 0x7810, MASK_VAL(2, 2, 0x0) }, \ 661 /* CTL_MCHBAR.ALWAYS_SNP_IDI */ \ 662 { PID_TUNIT, 0x7810, MASK_VAL(3, 3, 0x0) }, \ 663 /* CTL_MCHBAR.SNPINV */ \ 664 { PID_TUNIT, 0x7810, MASK_VAL(7, 7, 0x0) }, \ 665 /* CTL_MCHBAR.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ 666 { PID_TUNIT, 0x7810, MASK_VAL(18, 18, 0x0) }, \ 667 /* CTL_MCHBAR.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ 668 { PID_TUNIT, 0x7810, MASK_VAL(19, 19, 0x0) }, \ 669 /* CTL_MCHBAR.DISABLE_SNOOPING_GT */ \ 670 { PID_TUNIT, 0x7810, MASK_VAL(20, 20, 0x0) }, \ 671 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ 672 { PID_TUNIT, 0x781c, MASK_VAL(0, 0, 0x1) }, \ 673 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ 674 { PID_TUNIT, 0x781c, MASK_VAL(1, 1, 0x1) }, \ 675 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ 676 { PID_TUNIT, 0x781c, MASK_VAL(2, 2, 0x0) }, \ 677 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ 678 { PID_TUNIT, 0x781c, MASK_VAL(3, 3, 0x0) }, \ 679 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ 680 { PID_TUNIT, 0x781c, MASK_VAL(4, 4, 0x1) }, \ 681 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ 682 { PID_TUNIT, 0x781c, MASK_VAL(5, 5, 0x1) }, \ 683 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ 684 { PID_TUNIT, 0x781c, MASK_VAL(6, 6, 0x1) }, \ 685 /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ 686 { PID_TUNIT, 0x781c, MASK_VAL(7, 7, 0x1) }, \ 687 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ 688 { PID_TUNIT, 0x7820, MASK_VAL(0, 0, 0x1) }, \ 689 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ 690 { PID_TUNIT, 0x7820, MASK_VAL(1, 1, 0x1) }, \ 691 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ 692 { PID_TUNIT, 0x7820, MASK_VAL(2, 2, 0x0) }, \ 693 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ 694 { PID_TUNIT, 0x7820, MASK_VAL(3, 3, 0x0) }, \ 695 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ 696 { PID_TUNIT, 0x7820, MASK_VAL(4, 4, 0x1) }, \ 697 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ 698 { PID_TUNIT, 0x7820, MASK_VAL(5, 5, 0x1) }, \ 699 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ 700 { PID_TUNIT, 0x7820, MASK_VAL(6, 6, 0x1) }, \ 701 /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ 702 { PID_TUNIT, 0x7820, MASK_VAL(7, 7, 0x1) }, \ 703 /* T_CR_CTL.ALWAYS_SNP_PII2 */ \ 704 { PID_TUNIT, 0x523c, MASK_VAL(0, 0, 0x0) }, \ 705 /* T_CR_CTL.DIS_LIVE_BRAM_BYP_IDI */ \ 706 { PID_TUNIT, 0x523c, MASK_VAL(2, 2, 0x0) }, \ 707 /* T_CR_CTL.ALWAYS_SNP_IDI */ \ 708 { PID_TUNIT, 0x523c, MASK_VAL(3, 3, 0x0) }, \ 709 /* T_CR_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ 710 { PID_TUNIT, 0x523c, MASK_VAL(18, 18, 0x0) }, \ 711 /* T_CR_CTL.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ 712 { PID_TUNIT, 0x523c, MASK_VAL(19, 19, 0x0) }, \ 713 /* T_CR_CTL.DISABLE_SNOOPING_GT */ \ 714 { PID_TUNIT, 0x523c, MASK_VAL(20, 20, 0x0) }, \ 715 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ 716 { PID_TUNIT, 0x5288, MASK_VAL(0, 0, 0x1) }, \ 717 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ 718 { PID_TUNIT, 0x5288, MASK_VAL(1, 1, 0x1) }, \ 719 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ 720 { PID_TUNIT, 0x5288, MASK_VAL(2, 2, 0x0) }, \ 721 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ 722 { PID_TUNIT, 0x5288, MASK_VAL(3, 3, 0x0) }, \ 723 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ 724 { PID_TUNIT, 0x5288, MASK_VAL(4, 4, 0x1) }, \ 725 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ 726 { PID_TUNIT, 0x5288, MASK_VAL(5, 5, 0x1) }, \ 727 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ 728 { PID_TUNIT, 0x5288, MASK_VAL(6, 6, 0x1) }, \ 729 /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ 730 { PID_TUNIT, 0x5288, MASK_VAL(7, 7, 0x1) }, \ 731 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ 732 { PID_TUNIT, 0x528c, MASK_VAL(0, 0, 0x1) }, \ 733 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ 734 { PID_TUNIT, 0x528c, MASK_VAL(1, 1, 0x1) }, \ 735 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ 736 { PID_TUNIT, 0x528c, MASK_VAL(2, 2, 0x0) }, \ 737 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ 738 { PID_TUNIT, 0x528c, MASK_VAL(3, 3, 0x0) }, \ 739 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ 740 { PID_TUNIT, 0x528c, MASK_VAL(4, 4, 0x1) }, \ 741 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ 742 { PID_TUNIT, 0x528c, MASK_VAL(5, 5, 0x1) }, \ 743 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ 744 { PID_TUNIT, 0x528c, MASK_VAL(6, 6, 0x1) }, \ 745 /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ 746 { PID_TUNIT, 0x528c, MASK_VAL(7, 7, 0x1) } 747 748 #define VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ 749 AUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT, \ 750 BUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT, \ 751 TUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT 752 753 #define VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ 754 AUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT, \ 755 BUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT, \ 756 TUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT 757 758 #define VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ 759 AUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT, \ 760 BUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT, \ 761 TUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT 762 763 #endif /* _SOC_APOLLOLAKE_PNPCONFIG_H_ */ 764