1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_PMIF_SPMI_H__ 4 #define __SOC_MEDIATEK_PMIF_SPMI_H__ 5 6 #include <soc/addressmap.h> 7 #include <soc/pmif.h> 8 #include <soc/spmi.h> 9 10 #define DEFAULT_VALUE_READ_TEST (0x5a) 11 #define DEFAULT_VALUE_WRITE_TEST (0xa5) 12 13 #define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG) 14 #define PMIF_CMD_PER_1_3 ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) 15 16 struct mtk_rgu_regs { 17 u32 reserved[36]; 18 u32 wdt_swsysrst2; 19 }; 20 check_member(mtk_rgu_regs, wdt_swsysrst2, 0x90); 21 22 struct mtk_spmi_mst_reg { 23 u32 op_st_ctrl; 24 u32 grp_id_en; 25 u32 op_st_sta; 26 u32 mst_sampl; 27 u32 mst_req_en; 28 u32 rcs_ctrl; 29 u32 reserved1[10]; 30 u32 rec_ctrl; 31 u32 rec0; 32 u32 rec1; 33 u32 rec2; 34 u32 rec3; 35 u32 rec4; 36 u32 reserved2[41]; 37 u32 mst_dbg; 38 }; 39 40 check_member(mtk_spmi_mst_reg, rec_ctrl, 0x40); 41 check_member(mtk_spmi_mst_reg, mst_dbg, 0xfc); 42 43 #define mtk_rug ((struct mtk_rgu_regs *)RGU_BASE) 44 #define mtk_spmi_mst ((struct mtk_spmi_mst_reg *)SPMI_MST_BASE) 45 46 struct cali { 47 unsigned int dly; 48 unsigned int pol; 49 }; 50 51 enum { 52 SPMI_CK_NO_DLY = 0, 53 SPMI_CK_DLY_1T, 54 }; 55 56 enum { 57 SPMI_CK_POL_NEG = 0, 58 SPMI_CK_POL_POS, 59 }; 60 61 enum spmi_regs { 62 SPMI_OP_ST_CTRL, 63 SPMI_GRP_ID_EN, 64 SPMI_OP_ST_STA, 65 SPMI_MST_SAMPL, 66 SPMI_MST_REQ_EN, 67 SPMI_REC_CTRL, 68 SPMI_REC0, 69 SPMI_REC1, 70 SPMI_REC2, 71 SPMI_REC3, 72 SPMI_REC4, 73 SPMI_MST_DBG 74 }; 75 76 /* MT6315 registers */ 77 enum { 78 MT6315_BASE = 0x0, 79 MT6315_READ_TEST = MT6315_BASE + 0x9, 80 MT6315_READ_TEST_1 = MT6315_BASE + 0xb, 81 }; 82 83 #define MT6315_DEFAULT_VALUE_READ 0x15 84 85 extern const struct spmi_device spmi_dev[]; 86 extern const size_t spmi_dev_cnt; 87 88 int pmif_spmi_init(struct pmif *arb); 89 int spmi_config_master(void); 90 void pmif_spmi_iocfg(void); 91 void pmif_spmi_config(struct pmif *arb, int mstid); 92 #endif /* __SOC_MEDIATEK_PMIF_SPMI_H__ */ 93