1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_PLL_COMMON_H 4 #define SOC_MEDIATEK_PLL_COMMON_H 5 6 #include <device/mmio.h> 7 #include <soc/addressmap.h> 8 #include <types.h> 9 10 /* These need to be macros for use in static initializers. */ 11 #define mtk_topckgen ((struct mtk_topckgen_regs *)CKSYS_BASE) 12 #define mtk_apmixed ((struct mtk_apmixed_regs *)APMIXED_BASE) 13 14 #define PLL_PWR_ON (1 << 0) 15 #define PLL_EN (1 << 0) 16 #define PLL_ISO (1 << 1) 17 #define PLL_RSTB_SHIFT (24) 18 #define NO_RSTB_SHIFT (255) 19 #define PLL_PCW_CHG (1 << 31) 20 #define PLL_POSTDIV_MASK 0x7 21 22 struct mux { 23 void *reg; 24 void *set_reg; 25 void *clr_reg; 26 void *upd_reg; 27 u8 mux_shift; 28 u8 mux_width; 29 u8 upd_shift; 30 }; 31 32 struct pll { 33 void *reg; 34 void *pwr_reg; 35 void *div_reg; 36 void *pcw_reg; 37 const u32 *div_rate; 38 u8 rstb_shift; 39 u8 pcwbits; 40 u8 div_shift; 41 u8 pcw_shift; 42 }; 43 44 #define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \ 45 _pcw_reg, _pcw_shift, _div_rate) \ 46 [_id] = { \ 47 .reg = &mtk_apmixed->_reg, \ 48 .pwr_reg = &mtk_apmixed->_pwr_reg, \ 49 .rstb_shift = _rstb, \ 50 .pcwbits = _pcwbits, \ 51 .div_reg = &mtk_apmixed->_div_reg, \ 52 .div_shift = _div_shift, \ 53 .pcw_reg = &mtk_apmixed->_pcw_reg, \ 54 .pcw_shift = _pcw_shift, \ 55 .div_rate = _div_rate, \ 56 } 57 58 /* every PLL can share the same POWER_EN/ISO_EN/EN bits, use the common BITFIELD macro */ 59 DEFINE_BIT(PLL_ENABLE, 0) 60 61 DEFINE_BIT(PLL_POWER_ENABLE, 0) 62 DEFINE_BIT(PLL_ISO_ENABLE, 1) 63 DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0) 64 65 DEFINE_BITFIELD(PLL_CON1, 31, 0) 66 67 /* PLL internal interface */ 68 void pll_set_pcw_change(const struct pll *pll); 69 void pll_mux_set_sel(const struct mux *mux, u32 sel); 70 int pll_set_rate(const struct pll *pll, u32 rate); 71 72 /* PLL internal interface */ 73 void mt_pll_init(void); 74 void mt_pll_raise_little_cpu_freq(u32 freq); 75 void mt_pll_raise_cci_freq(u32 freq); 76 void mt_pll_set_tvd_pll1_freq(u32 freq); 77 void mt_pll_edp_mux_set_sel(u32 sel); 78 void mt_pll_spmi_mux_select(void); 79 void mt_pll_set_usb_clock(void); 80 81 enum fmeter_type { 82 FMETER_ABIST = 0, 83 FMETER_CKGEN, 84 }; 85 u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id); 86 87 #endif 88