1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_STONEYRIDGE_NORTHBRIDGE_H 4 #define AMD_STONEYRIDGE_NORTHBRIDGE_H 5 6 #include <device/device.h> 7 #include <types.h> 8 9 /* D0F0 - Root Complex */ 10 11 /* NB IOAPIC registers */ 12 #define NB_IOAPIC_INDEX 0xf8 13 #define NB_IOAPIC_DATA 0xfc 14 #define NB_IOAPIC_FEATURE_CTRL 0x00 15 #define NB_IOAPIC_ADDRESS_LOW 0x01 16 #define NB_IOAPIC_ADDRESS_HIGH 0x02 17 #define NB_IOAPIC_GBIF_IRR 0x0f 18 #define NB_IOAPIC_BR0_IRR 0x10 19 #define NB_IOAPIC_BR1_IRR 0x11 20 #define NB_IOAPIC_BR2_IRR 0x12 21 #define NB_IOAPIC_BR3_IRR 0x13 22 #define NB_IOAPIC_BR4_IRR 0x14 23 #define NB_IOAPIC_APG_IRR 0x2f 24 #define NB_IOAPIC_SPG_IRR 0x30 25 #define NB_IOAPIC_SER_IRQ_IRR 0x31 26 #define NB_IOAPIC_SCRATCH0 0x3e 27 #define NB_IOAPIC_SCRATCH1 0x3f 28 29 /* D1F1 - HDA Configuration Registers */ 30 #define HDA_DEV_CTRL_STATUS 0x60 31 #define HDA_NO_SNOOP_EN BIT(11) 32 33 /* D18F0 - HT Configuration Registers */ 34 #define D18F0_NODE_ID 0x60 35 #define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */ 36 # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ 37 #define HT_INIT_CONTROL 0x6c 38 # define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10)) 39 # define HTIC_COLD_RST_DET BIT(4) 40 41 /* D18F1 - Address Map Registers */ 42 43 /* MMIO base and limit */ 44 #define D18F1_MMIO_BASE0_LO 0x80 45 # define MMIO_WE (1 << 1) 46 # define MMIO_RE (1 << 0) 47 #define D18F1_MMIO_LIMIT0_LO 0x84 48 # define MMIO_NP (1 << 7) 49 #define D18F1_IO_BASE0_LO 0xc0 50 #define D18F1_IO_BASE1_LO 0xc8 51 #define D18F1_IO_BASE2_LO 0xd0 52 #define D18F1_IO_BASE3_LO 0xd8 53 #define D18F1_MMIO_BASE7_LO 0xb8 54 #define D18F1_MMIO_BASELIM0_HI 0x180 55 #define D18F1_MMIO_BASE8_LO 0x1a0 56 #define D18F1_MMIO_LIMIT8_LO 0x1a4 57 #define D18F1_MMIO_BASE11_LO 0x1b8 58 #define D18F1_MMIO_BASELIM8_HI 0x1c0 59 #define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \ 60 ? D18F1_MMIO_BASE0_LO \ 61 : D18F1_MMIO_BASE8_LO \ 62 - 8 * sizeof(uint64_t))) 63 #define NB_MMIO_LIMIT_LO(reg) (NB_MMIO_BASE_LO(reg) + sizeof(uint32_t)) 64 #define NB_MMIO_BASELIM_HI(reg) ((reg) * sizeof(uint32_t) + (((reg) < 8) \ 65 ? D18F1_MMIO_BASELIM0_HI \ 66 : D18F1_MMIO_BASELIM8_HI \ 67 - 8 * sizeof(uint32_t))) 68 /* I/O base and limit */ 69 #define D18F1_IO_BASE0 0xc0 70 # define IO_WE (1 << 1) 71 # define IO_RE (1 << 0) 72 #define D18F1_IO_LIMIT0 0xc4 73 #define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0) 74 #define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t)) 75 76 #define D18F1_DRAM_HOLE 0xf0 77 # define DRAM_HOIST_VALID (1 << 1) 78 # define DRAM_HOLE_VALID (1 << 0) 79 #define D18F1_VGAEN 0xf4 80 # define VGA_ADDR_ENABLE (1 << 0) 81 82 /* D18F5 */ 83 #define NB_CAPABILITIES2 0x84 84 #define CMP_CAP_MASK 0xff 85 86 void domain_enable_resources(struct device *dev); 87 void domain_read_resources(struct device *dev); 88 void fam15_finalize(void *chip_info); 89 90 #endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */ 91