1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT6358_H__ 4 #define __SOC_MEDIATEK_MT6358_H__ 5 6 #include <types.h> 7 8 enum { 9 PMIC_SWCID = 0x000a, 10 PMIC_VM_MODE = 0x004e, 11 PMIC_TOP_CKPDN_CON0_SET = 0x010e, 12 PMIC_TOP_CKPDN_CON0_CLR = 0x0110, 13 PMIC_TOP_CKHWEN_CON0_SET = 0x012c, 14 PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, 15 PMIC_TOP_RST_MISC = 0x014c, 16 PMIC_TOP_RST_MISC_SET = 0x014e, 17 PMIC_TOP_RST_MISC_CLR = 0x0150, 18 PMIC_OTP_CON0 = 0x038a, 19 PMIC_OTP_CON8 = 0x039a, 20 PMIC_OTP_CON11 = 0x03a0, 21 PMIC_OTP_CON12 = 0x03a2, 22 PMIC_OTP_CON13 = 0x03a4, 23 PMIC_TOP_TMA_KEY = 0x03a8, 24 PMIC_PWRHOLD = 0x0a08, 25 PMIC_CPSDSA4 = 0x0a2e, 26 PMIC_VCORE_OP_EN = 0x1490, 27 PMIC_VCORE_DBG0 = 0x149e, 28 PMIC_VCORE_VOSEL = 0x14aa, 29 PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, 30 PMIC_VDRAM1_OP_EN = 0x1610, 31 PMIC_VDRAM1_DBG0 = 0x161e, 32 PMIC_VDRAM1_VOSEL = 0x1626, 33 PMIC_SMPS_ANA_CON0 = 0x1808, 34 PMIC_VDDQ_OP_EN = 0x1b16, 35 PMIC_VSIM2_ANA_CON0 = 0x1e30, 36 PMIC_VDDQ_ELR_0 = 0x1ec4, 37 }; 38 39 struct pmic_setting { 40 unsigned short addr; 41 unsigned short val; 42 unsigned short mask; 43 unsigned char shift; 44 }; 45 46 void mt6358_init(void); 47 void pmic_set_power_hold(bool enable); 48 void pmic_set_vsim2_cali(unsigned int vsim2_mv); 49 void pmic_init_scp_voltage(void); 50 unsigned int pmic_get_vcore_vol(void); 51 void pmic_set_vcore_vol(unsigned int vcore_uv); 52 unsigned int pmic_get_vdram1_vol(void); 53 void pmic_set_vdram1_vol(unsigned int vdram_uv); 54 unsigned int pmic_get_vddq_vol(void); 55 void pmic_set_vddq_vol(unsigned int vddq_uv); 56 57 #endif /* __SOC_MEDIATEK_MT6358_H__ */ 58