1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_IIO_H_ 4 #define _SOC_IIO_H_ 5 6 #include <soc/soc_util.h> 7 8 #include <fsp/util.h> 9 #include <FspmUpd.h> 10 #include <IioPcieConfigUpd.h> 11 12 #define CB_IIO_BIFURCATE_xxxxxxxx IIO_BIFURCATE_xxxxxxxx 13 #define CB_IIO_BIFURCATE_x4x4x4x4 IIO_BIFURCATE_x4x4x4x4 14 #define CB_IIO_BIFURCATE_x8xxx4x4 IIO_BIFURCATE_x4x4xxx8 15 #define CB_IIO_BIFURCATE_x4x4x8xx IIO_BIFURCATE_xxx8x4x4 16 #define CB_IIO_BIFURCATE_x8xxx8xx IIO_BIFURCATE_xxx8xxx8 17 #define CB_IIO_BIFURCATE_x16xxxxx IIO_BIFURCATE_xxxxxx16 18 #define CB_IIO_BIFURCATE_x8x4x2x2 IIO_BIFURCATE_x2x2x4x8 19 #define CB_IIO_BIFURCATE_x8x2x2x4 IIO_BIFURCATE_x4x2x2x8 20 #define CB_IIO_BIFURCATE_x4x2x2x8 IIO_BIFURCATE_x8x2x2x4 21 #define CB_IIO_BIFURCATE_x2x2x4x8 IIO_BIFURCATE_x8x4x2x2 22 #define CB_IIO_BIFURCATE_x4x4x4x2x2 IIO_BIFURCATE_x2x2x4x4x4 23 #define CB_IIO_BIFURCATE_x4x4x2x2x4 IIO_BIFURCATE_x4x2x2x4x4 24 #define CB_IIO_BIFURCATE_x4x2x2x4x4 IIO_BIFURCATE_x4x4x2x2x4 25 #define CB_IIO_BIFURCATE_x2x2x4x4x4 IIO_BIFURCATE_x4x4x4x2x2 26 #define CB_IIO_BIFURCATE_x8x2x2x2x2 IIO_BIFURCATE_x2x2x2x2x8 27 #define CB_IIO_BIFURCATE_x2x2x2x2x8 IIO_BIFURCATE_x8x2x2x2x2 28 #define CB_IIO_BIFURCATE_x4x4x2x2x2x2 IIO_BIFURCATE_x2x2x2x2x4x4 29 #define CB_IIO_BIFURCATE_x4x2x2x4x2x2 IIO_BIFURCATE_x2x2x4x2x2x4 30 #define CB_IIO_BIFURCATE_x2x2x4x4x2x2 IIO_BIFURCATE_x2x2x4x4x2x2 31 #define CB_IIO_BIFURCATE_x4x2x2x2x2x4 IIO_BIFURCATE_x4x2x2x2x2x4 32 #define CB_IIO_BIFURCATE_x2x2x4x2x2x4 IIO_BIFURCATE_x4x2x2x4x2x2 33 #define CB_IIO_BIFURCATE_x2x2x2x2x4x4 IIO_BIFURCATE_x4x4x2x2x2x2 34 #define CB_IIO_BIFURCATE_x4x2x2x2x2x2x2 IIO_BIFURCATE_x2x2x2x2x2x2x4 35 #define CB_IIO_BIFURCATE_x2x2x4x2x2x2x2 IIO_BIFURCATE_x2x2x2x2x4x2x2 36 #define CB_IIO_BIFURCATE_x2x2x2x2x4x2x2 IIO_BIFURCATE_x2x2x4x2x2x2x2 37 #define CB_IIO_BIFURCATE_x2x2x2x2x2x2x4 IIO_BIFURCATE_x4x2x2x2x2x2x2 38 #define CB_IIO_BIFURCATE_x2x2x2x2x2x2x2x2 IIO_BIFURCATE_x2x2x2x2x2x2x2x2 39 #define CB_IIO_BIFURCATE_AUTO IIO_BIFURCATE_AUTO 40 41 struct iio_port_config { 42 uint8_t vpp_address; // SMBUS address of IO expander which provides VPP register 43 uint8_t vpp_port; // Port or bank on IoExpander which provides VPP register 44 uint8_t vpp_mux_address; // SMBUS address of MUX used to access VPP 45 uint8_t vpp_mux_channel; // Channel of the MUX used to access VPP 46 47 uint8_t slot_eip:1; // Electromechanical Interlock Present - 48 // Slot Capabilities (D0-10 / F0 / R0xA4 / B17) 49 uint8_t slot_hps:1; // Hot Plug surprise supported - 50 // Slot Capabilities (D0-10 / F0 / R0xA4 / B5) 51 uint8_t slot_pind:1; // Power Indicator Present - 52 // Slot Capabilities (D0-10 / F0 / R0xA4 / B4) 53 uint8_t slot_aind:1; // Attention Inductor Present - 54 // Slot Capabilities (D0-10 / F0 / R0xA4 / B3) 55 uint8_t slot_pctl:1; // Power Controller Present - 56 // Slot Capabilities (D0-10 / F0 / R0xA4 / B1) 57 uint8_t slot_abtn:1; // Attention Button Present - 58 // Slot Capabilities (D0-10 / F0 / R0xA4 / B0) 59 uint8_t slot_rsvd:2; // Reserved 60 61 uint8_t vpp_enabled:1; // If VPP is supported on given port 62 uint8_t vpp_exp_type:1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE 63 // for values definitions) 64 65 uint8_t slot_implemented:1; 66 uint8_t reserved:4; 67 68 uint16_t hot_plug:1; // If hotplug is supported on slot connected to this port 69 uint16_t mrl_sensor_present:1; // If MRL is present on slot connected to this port 70 uint16_t slot_power_limit_scale:2; // Slot Power Scale for slot connected to this port 71 uint16_t slot_power_limit_value:12; // Slot Power Value for slot connected to this port 72 73 uint16_t physical_slot_number; // Slot number for slot connected to this port 74 }; 75 76 struct iio_pe_config { 77 uint8_t socket; 78 IIO_PACKAGE_PE pe; 79 IIO_BIFURCATION bifurcation; 80 uint8_t cxl_support:1; 81 uint8_t reserved:7; 82 struct iio_port_config port_config[MAX_IIO_PORTS_PER_STACK]; 83 }; 84 85 /* 86 * {_IIO_PE_CFG_STRUCT(socket, pe, bif, cxl) { 87 * _IIO_PORT_CFG_STRUCT(vppen vppex vaddr vport vmuxa vmuxc ...), 88 * _IIO_PORT_CFG_STRUCT(..), 89 * ... 90 * _IIO_PORT_CFG_STRUCT(..) //MAX_IIO_PORTS_PER_STACK port configs 91 * }} 92 */ 93 94 #define PE_TYPE_CXL 1 95 #define PE_TYPE_PCIE 0 96 97 #define _IIO_PE_CFG_STRUCT(s, p, bif, cxl) \ 98 .socket = (s),\ 99 .pe = (p),\ 100 .bifurcation = (bif),\ 101 .cxl_support = (cxl),\ 102 .reserved = 0,\ 103 .port_config = 104 105 /* TODO: to update rsv1 - rsv5 after SoC launch */ 106 #define _IIO_PORT_CFG_STRUCT(vppen, vppex, vaddr, vport, vmuxa, vmuxc,\ 107 slteip, slthps, sltpind, sltaind, sltpctl, sltabtn, hotp, mrlsp,\ 108 sltimpl, sltpls, sltplv, psn,\ 109 rsv1, rsv2, rsv3, rsv4, rsv5) {\ 110 .vpp_enabled = (vppen),\ 111 .vpp_exp_type = (vppex),\ 112 .vpp_address = (vaddr),\ 113 .vpp_port = (vport),\ 114 .vpp_mux_address = (vmuxa),\ 115 .vpp_mux_channel = (vmuxc),\ 116 .slot_eip = (slteip),\ 117 .slot_hps = (slthps),\ 118 .slot_pind = (sltpind),\ 119 .slot_aind = (sltaind),\ 120 .slot_pctl = (sltpctl),\ 121 .slot_abtn = (sltabtn),\ 122 .slot_rsvd = 0,\ 123 .slot_implemented = (sltimpl),\ 124 .reserved = 0,\ 125 .hot_plug = (hotp),\ 126 .mrl_sensor_present = (mrlsp),\ 127 .slot_power_limit_scale = (sltpls),\ 128 .slot_power_limit_value = (sltplv),\ 129 .physical_slot_number = (psn)\ 130 } 131 132 #define _IIO_PORT_CFG_STRUCT_DISABLED \ 133 _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\ 134 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0) 135 136 #define _IIO_PORT_CFG_STRUCT_X8 _IIO_PORT_CFG_STRUCT 137 #define _IIO_PORT_CFG_STRUCT_X4 _IIO_PORT_CFG_STRUCT 138 #define _IIO_PORT_CFG_STRUCT_X2 _IIO_PORT_CFG_STRUCT 139 140 #define _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn)\ 141 _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\ 142 0x0, 0x0, 0x0, 0x1, sltpls, sltplv, psn, 0x0, 0x0, 0x0, 0x0, 0x0) 143 144 #define _IIO_PORT_CFG_STRUCT_BASIC_X8 _IIO_PORT_CFG_STRUCT_BASIC 145 #define _IIO_PORT_CFG_STRUCT_BASIC_X4 _IIO_PORT_CFG_STRUCT_BASIC 146 #define _IIO_PORT_CFG_STRUCT_BASIC_X2 _IIO_PORT_CFG_STRUCT_BASIC 147 148 void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_table, 149 unsigned int num_entries); 150 151 const struct iio_pe_config *get_iio_config_table(int *size); 152 153 #endif /* _SOC_IIO_H_ */ 154