1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DENVERTON_NS_GPIO_H_ 4 #define _DENVERTON_NS_GPIO_H_ 5 6 #include <soc/gpio_defs.h> 7 8 #ifndef __ACPI__ 9 #include <stdint.h> 10 #include <stddef.h> 11 12 // 13 // Structure for storing information about registers offset, community, 14 // maximal pad number for available groups 15 // 16 struct GPIO_GROUP_INFO { 17 uint32_t Community; 18 uint32_t PadOwnOffset; 19 uint32_t HostOwnOffset; 20 uint32_t GpiIsOffset; 21 uint32_t GpiIeOffset; 22 uint32_t GpiGpeStsOffset; 23 uint32_t GpiGpeEnOffset; 24 uint32_t SmiStsOffset; 25 uint32_t SmiEnOffset; 26 uint32_t NmiStsOffset; 27 uint32_t NmiEnOffset; 28 uint32_t PadCfgLockOffset; 29 uint32_t PadCfgLockTxOffset; 30 uint32_t PadCfgOffset; 31 uint32_t PadPerGroup; 32 }; 33 34 // 35 // If in GPIO_GROUP_INFO structure certain register doesn't exist 36 // it will have value equal to NO_REGISTER_FOR_PROPERTY 37 // 38 #define NO_REGISTER_FOR_PROPERTY (~0u) 39 40 // 41 // Below defines are based on GPIO_CONFIG structure fields 42 // 43 #define GPIO_CONF_PAD_MODE_MASK 0xF 44 #define GPIO_CONF_PAD_MODE_BIT_POS 0 45 #define GPIO_CONF_HOST_OWN_MASK 0x3 46 #define GPIO_CONF_HOST_OWN_BIT_POS 0 47 #define GPIO_CONF_DIR_MASK 0x7 48 #define GPIO_CONF_DIR_BIT_POS 0 49 #define GPIO_CONF_INV_MASK 0x18 50 #define GPIO_CONF_INV_BIT_POS 3 51 #define GPIO_CONF_OUTPUT_MASK 0x3 52 #define GPIO_CONF_OUTPUT_BIT_POS 0 53 #define GPIO_CONF_INT_ROUTE_MASK 0x1F 54 #define GPIO_CONF_INT_ROUTE_BIT_POS 0 55 #define GPIO_CONF_INT_TRIG_MASK 0xE0 56 #define GPIO_CONF_INT_TRIG_BIT_POS 5 57 #define GPIO_CONF_RESET_MASK 0x7 58 #define GPIO_CONF_RESET_BIT_POS 0 59 #define GPIO_CONF_TERM_MASK 0x1F 60 #define GPIO_CONF_TERM_BIT_POS 0 61 #define GPIO_CONF_PADTOL_MASK 0x60 62 #define GPIO_CONF_PADTOL_BIT_POS 5 63 #define GPIO_CONF_LOCK_MASK 0x7 64 #define GPIO_CONF_LOCK_BIT_POS 0 65 #define GPIO_CONF_RXRAW_MASK 0x3 66 #define GPIO_CONF_RXRAW_BIT_POS 0 67 68 /** 69 GPIO configuration structure used for pin programming. 70 Structure contains fields that can be used to configure pad. 71 **/ 72 struct GPIO_CONFIG { 73 /** 74 Pad Mode 75 Pad can be set as GPIO or one of its native functions. 76 When in native mode setting Direction (except Inversion), OutputState, 77 InterruptConfig and Host Software Pad Ownership are unnecessary. 78 Refer to definition of GPIO_PAD_MODE. 79 Refer to EDS for each native mode according to the pad. 80 **/ 81 uint32_t PadMode : 4; 82 /** 83 Host Software Pad Ownership 84 Set pad to ACPI mode or GPIO Driver Mode. 85 Refer to definition of GPIO_HOSTSW_OWN. 86 **/ 87 uint32_t HostSoftPadOwn : 2; 88 /** 89 GPIO Direction 90 Can choose between In, In with inversion Out, both In and Out, both In 91 with inversion and out or disabling both. 92 Refer to definition of GPIO_DIRECTION for supported settings. 93 **/ 94 uint32_t Direction : 5; 95 /** 96 Output State 97 Set Pad output value. 98 Refer to definition of GPIO_OUTPUT_STATE for supported settings. 99 This setting takes place when output is enabled. 100 **/ 101 uint32_t OutputState : 2; 102 /** 103 GPIO Interrupt Configuration 104 Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting 105 is applicable only if GPIO is in input mode. 106 If GPIO is set to cause an SCI then also Gpe is enabled for this pad. 107 Refer to definition of GPIO_INT_CONFIG for supported settings. 108 **/ 109 uint32_t InterruptConfig : 8; 110 /** 111 GPIO Power Configuration. 112 This setting controls Pad Reset Configuration. 113 Refer to definition of GPIO_RESET_CONFIG for supported settings. 114 **/ 115 uint32_t PowerConfig : 4; 116 117 /** 118 GPIO Electrical Configuration 119 This setting controls pads termination and voltage tolerance. 120 Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. 121 **/ 122 uint32_t ElectricalConfig : 7; 123 124 /** 125 GPIO Lock Configuration 126 This setting controls pads lock. 127 Refer to definition of GPIO_LOCK_CONFIG for supported settings. 128 **/ 129 uint32_t LockConfig : 3; 130 /** 131 Additional GPIO configuration 132 Refer to definition of GPIO_OTHER_CONFIG for supported settings. 133 **/ 134 uint32_t OtherSettings : 2; 135 uint32_t RsvdBits : 27; ///< Reserved bits for future extension 136 } __packed; 137 138 typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; 139 140 /// 141 /// GPIO Pad Mode 142 /// 143 typedef enum { 144 GpioPadModeGpio = 0x1, 145 GpioPadModeNative1 = 0x3, 146 GpioPadModeNative2 = 0x5, 147 GpioPadModeNative3 = 0x7, 148 GpioPadModeNative4 = 0x9 149 } GPIO_PAD_MODE; 150 151 /// 152 /// Host Software Pad Ownership modes 153 /// 154 typedef enum { 155 GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified 156 GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI 157 GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO 158 } GPIO_HOSTSW_OWN; 159 160 /// 161 /// GPIO Direction 162 /// 163 typedef enum { 164 GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified 165 GpioDirInOut = 166 (0x1 | (0x1 << 3)), ///< Set pad for both output and input 167 GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and 168 ///input with inversion 169 GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only 170 GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion 171 GpioDirOut = 0x5, ///< Set pad for output only 172 GpioDirNone = 0x7 ///< Disable both output and input 173 } GPIO_DIRECTION; 174 175 /// 176 /// GPIO Output State 177 /// 178 typedef enum { 179 GpioOutDefault = 0x0, ///< Leave output value unmodified 180 GpioOutLow = 0x1, ///< Set output to low 181 GpioOutHigh = 0x3 ///< Set output to high 182 } GPIO_OUTPUT_STATE; 183 184 /// 185 /// GPIO interrupt configuration 186 /// This setting is applicable only if GPIO is in input mode. 187 /// GPIO_INT_CONFIG allows to choose which interrupt is generated 188 /// (IOxAPIC/SCI/SMI/NMI) 189 /// and how it is triggered (edge or level). 190 /// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to 191 /// GpioIntBothEdgecan 192 /// to describe an interrupt e.g. GpioIntApic | GpioIntLevel 193 /// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. 194 /// Not all GPIO are capable of generating an SMI or NMI interrupt 195 /// 196 197 typedef enum { 198 GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified 199 GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation 200 GpioIntNmi = 0x3, ///< Enable NMI interrupt only 201 GpioIntSmi = 0x5, ///< Enable SMI interrupt only 202 GpioIntSci = 0x9, ///< Enable SCI interrupt only 203 GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only 204 GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered 205 GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of 206 ///edge depends on input inversion) 207 GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger 208 GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered 209 } GPIO_INT_CONFIG; 210 211 /// 212 /// GPIO Power Configuration 213 /// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified 214 /// Pad Register fields). 215 /// 216 typedef enum { 217 GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified 218 GpioResetPwrGood = 0x1, ///< Powergood reset 219 GpioResetDeep = 0x3, ///< Deep GPIO Reset 220 GpioResetNormal = 0x5, ///< GPIO Reset 221 GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) 222 } GPIO_RESET_CONFIG; 223 224 /// 225 /// GPIO Electrical Configuration 226 /// Set GPIO termination and Pad Tolerance (applicable only for some pads) 227 /// Field from GpioTermDefault to GpioTermNative can be OR'ed with 228 /// GpioTolerance1v8. 229 /// 230 typedef enum { 231 GpioTermDefault = 0x0, ///< Leave termination setting unmodified 232 GpioTermNone = 0x1, ///< none 233 GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down 234 GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down 235 GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up 236 GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up 237 GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up 238 GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up 239 GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up 240 GpioTermNative = 0x1F, ///< Native function controls pads termination 241 GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance 242 GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance 243 } GPIO_ELECTRICAL_CONFIG; 244 245 /// 246 /// GPIO LockConfiguration 247 /// Set GPIO configuration lock and output state lock 248 /// GpioLockPadConfig and GpioLockOutputState can be OR'ed 249 /// 250 typedef enum { 251 GpioLockDefault = 0x0, ///< Leave lock setting unmodified 252 GpioPadConfigLock = 0x3, ///< Lock Pad Configuration 253 GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value 254 } GPIO_LOCK_CONFIG; 255 256 /// 257 /// Other GPIO Configuration 258 /// GPIO_OTHER_CONFIG is used for less often settings and for future extensions 259 /// Supported settings: 260 /// - RX raw override to '1' - allows to override input value to '1' 261 /// This setting is applicable only if in input mode (both in GPIO and 262 /// native usage). 263 /// The override takes place at the internal pad state directly from buffer 264 /// and before the RXINV. 265 /// 266 typedef enum { 267 GpioRxRaw1Default = 0x0, ///< Use default input override value 268 GpioRxRaw1Dis = 0x1, ///< Don't override input 269 GpioRxRaw1En = 0x3 ///< Override input to '1' 270 } GPIO_OTHER_CONFIG; 271 272 // 273 // Possible values of Pad Ownership 274 // 275 typedef enum { 276 GpioPadOwnHost = 0x0, 277 GpioPadOwnCsme = 0x1, 278 GpioPadOwnIsh = 0x2, 279 } GPIO_PAD_OWN; 280 281 typedef uint32_t GPIO_PAD; 282 283 struct dnv_pad_config { 284 GPIO_PAD GpioPad; 285 struct GPIO_CONFIG GpioConfig; 286 }; 287 288 /* Configure GPIOs with mainboard provided settings */ 289 void gpio_configure_dnv_pads(const struct dnv_pad_config *gpio, size_t num); 290 291 #endif /* __ACPI__ */ 292 #endif /* _DENVERTON_NS_GPIO_H_ */ 293