1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_COMMON_DP_DPTX_H 4 #define SOC_MEDIATEK_COMMON_DP_DPTX_H 5 6 #define DPTX_TBC_BUF_READSTARTADRTHRD 0x08 7 #define ENABLE_DPTX_EF_MODE 0x1 8 #define DPTX_AUX_SET_ENAHNCED_FRAME 0x80 9 10 union misc_t { 11 struct { 12 u8 is_sync_clock : 1; 13 u8 color_format : 2; 14 u8 spec_def1 : 2; 15 u8 color_depth : 3; 16 u8 interlaced : 1; 17 u8 stereo_attr : 2; 18 u8 reserved : 3; 19 u8 is_vsc_sdp : 1; 20 u8 spec_def2 : 1; 21 } dp_misc; 22 u8 cmisc[2]; 23 }; 24 25 struct dptx_training_info { 26 bool sink_extcap_en; 27 bool tps3; 28 bool tps4; 29 bool sink_ssc_en; 30 bool dp_mstcap; 31 bool dp_mstbranch; 32 bool down_stream_port_present; 33 bool cr_done; 34 bool eq_done; 35 u8 sys_max_linkrate; 36 u8 linkrate; 37 u8 linklane_count; 38 u8 dpcd_rev; 39 u8 sink_count_num; 40 }; 41 42 struct dptx_info { 43 uint8_t depth; 44 uint8_t format; 45 uint8_t resolution; 46 }; 47 48 struct mtk_dp { 49 int id; 50 struct edid *edid; 51 u8 rx_cap[16]; 52 struct dptx_info info; 53 int state; 54 int state_pre; 55 struct dptx_training_info train_info; 56 int training_state; 57 u8 irq_status; 58 u32 min_clock; 59 u32 max_clock; 60 u32 max_hdisplay; 61 u32 max_vdisplay; 62 void *regs; 63 int disp_status; 64 bool power_on; 65 bool audio_enable; 66 bool video_enable; 67 bool dp_ready; 68 bool has_dsc; 69 bool has_fec; 70 bool dsc_enable; 71 bool enabled; 72 bool powered; 73 }; 74 75 int mtk_edp_init(struct edid *edid); 76 77 #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_H */ 78