1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_COMMON_DPM_H__ 4 #define __SOC_MEDIATEK_COMMON_DPM_H__ 5 6 #include <soc/addressmap.h> 7 #include <soc/mcu_common.h> 8 #include <types.h> 9 10 struct dpm_regs { 11 u32 sw_rstn; 12 u32 rsvd_0[3072]; 13 u32 mclk_div; 14 u32 rsvd_1[3071]; 15 u32 twam_window_len; 16 u32 twam_mon_type; 17 u32 rsvd_2[1022]; 18 u32 low_power_cfg_0; 19 u32 low_power_cfg_1; 20 u32 rsvd_3[1]; 21 u32 fsm_out_ctrl_0; 22 u32 rsvd_4[8]; 23 u32 fsm_cfg_1; 24 u32 low_power_cfg_3; 25 u32 dfd_dbug_0; 26 u32 rsvd_5[28]; 27 u32 status_4; 28 }; 29 30 check_member(dpm_regs, mclk_div, 0x3004); 31 check_member(dpm_regs, twam_window_len, 0x6004); 32 check_member(dpm_regs, low_power_cfg_0, 0x7004); 33 check_member(dpm_regs, low_power_cfg_1, 0x7008); 34 check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); 35 check_member(dpm_regs, fsm_cfg_1, 0x7034); 36 check_member(dpm_regs, low_power_cfg_3, 0x7038); 37 check_member(dpm_regs, dfd_dbug_0, 0x703C); 38 check_member(dpm_regs, status_4, 0x70B0); 39 40 #define DPM_SW_RSTN_RESET BIT(0) 41 #define DPM_MEM_RATIO_OFFSET 28 42 #define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET) 43 #define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET) 44 #define DRAMC_MCU_SRAM_ISOINT_B_LSB BIT(1) 45 #define DRAMC_MCU2_SRAM_ISOINT_B_LSB BIT(1) 46 #define DRAMC_MCU_SRAM_SLEEP_B_LSB BIT(4) 47 #define DRAMC_MCU2_SRAM_SLEEP_B_LSB BIT(4) 48 49 static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE; 50 51 void dpm_reset(struct mtk_mcu *mcu); 52 int dpm_init(void); 53 int dpm_4ch_para_setting(void); 54 int dpm_4ch_init(void); 55 56 #endif /* __SOC_MEDIATEK_COMMON_DPM_H__ */ 57