1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* Header file for Samsung DP (Display Port) interface driver. */ 4 5 #ifndef CPU_SAMSUNG_EXYNOS5250_DP_CORE_H 6 #define CPU_SAMSUNG_EXYNOS5250_DP_CORE_H 7 8 #define STREAM_ON_TIMEOUT 100 9 #define PLL_LOCK_TIMEOUT 10 10 #define DP_INIT_TRIES 10 11 #define MAX_CR_LOOP 5 12 #define MAX_EQ_LOOP 4 13 14 /* Link rate type */ 15 enum link_rate { 16 LINK_RATE_1_62GBPS = 0x06, 17 LINK_RATE_2_70GBPS = 0x0a 18 }; 19 20 /* Number of lanes supported */ 21 enum link_lane_count { 22 LANE_COUNT1 = 1, 23 LANE_COUNT2 = 2, 24 LANE_COUNT4 = 4 25 }; 26 27 /* Pre emphasis level */ 28 enum pre_emphasis_level { 29 PRE_EMPHASIS_LEVEL_0, 30 PRE_EMPHASIS_LEVEL_1, 31 PRE_EMPHASIS_LEVEL_2, 32 PRE_EMPHASIS_LEVEL_3, 33 }; 34 35 /* Type of color space */ 36 enum color_space { 37 COLOR_RGB, 38 COLOR_YCBCR422, 39 COLOR_YCBCR444 40 }; 41 42 /* Video input Bit Per Color */ 43 enum color_depth { 44 COLOR_6, 45 COLOR_8, 46 COLOR_10, 47 COLOR_12 48 }; 49 50 /* Type of YCbCr coefficient */ 51 enum color_coefficient { 52 COLOR_YCBCR601, 53 COLOR_YCBCR709 54 }; 55 56 /* Color range */ 57 enum dynamic_range { 58 VESA, 59 CEA 60 }; 61 62 /* Status of PLL clock */ 63 enum pll_status { 64 PLL_UNLOCKED, 65 PLL_LOCKED 66 }; 67 68 /* To choose type of m_value */ 69 enum clock_recovery_m_value_type { 70 CALCULATED_M, 71 REGISTER_M 72 }; 73 74 struct video_info { 75 enum color_space color_space; 76 enum dynamic_range dynamic_range; 77 enum color_coefficient ycbcr_coeff; 78 enum color_depth color_depth; 79 80 enum link_rate link_rate; 81 enum link_lane_count lane_count; 82 83 char *name; 84 85 unsigned int h_sync_polarity:1; 86 unsigned int v_sync_polarity:1; 87 unsigned int interlaced:1; 88 }; 89 90 struct link_train { 91 u8 link_rate; 92 u8 lane_count; 93 }; 94 95 struct s5p_dp_device { 96 unsigned int irq; 97 struct exynos5_dp *base; 98 struct video_info *video_info; 99 struct link_train link_train; 100 }; 101 102 /* s5p_dp_reg.c */ 103 104 /* 105 * Reset DP module 106 * 107 * param dp pointer to main s5p-dp structure 108 */ 109 void s5p_dp_reset(struct s5p_dp_device *dp); 110 /* 111 * Initialize DP to receive video stream 112 * 113 * param dp pointer to main s5p-dp structure 114 */ 115 void s5p_dp_init_video(struct s5p_dp_device *dp); 116 /* 117 * Check whether PLL is locked 118 * 119 * param dp pointer to main s5p-dp structure 120 * return Lock status 121 */ 122 unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp); 123 /* 124 * Initialize analog functions of DP 125 * 126 * param dp pointer to main s5p-dp structure 127 * return 0 on success 128 */ 129 int s5p_dp_init_analog_func(struct s5p_dp_device *dp); 130 /* 131 * Initialize DP for AUX transaction 132 * 133 * param dp pointer to main s5p-dp structure 134 */ 135 void s5p_dp_init_aux(struct s5p_dp_device *dp); 136 137 /* 138 * Start an AUX transaction. 139 * 140 * param dp pointer to main s5p-dp structure 141 */ 142 int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp); 143 144 /* 145 * Write a byte to DPCD register 146 * 147 * param dp pointer to main s5p-dp structure 148 * param reg_addr DPCD register to be written 149 * param data byte data to be written 150 * return write status 151 */ 152 int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, 153 unsigned int reg_addr, 154 unsigned char data); 155 /* 156 * Read a byte from DPCD register 157 * 158 * param dp pointer to main s5p-dp structure 159 * param reg_addr DPCD register to read 160 * param data read byte data 161 * return read status 162 */ 163 int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, 164 unsigned int reg_addr, 165 unsigned char *data); 166 /* 167 * Initialize DP video functions 168 * 169 * param dp pointer to main s5p-dp structure 170 */ 171 //void s5p_dp_init_video(struct s5p_dp_device *dp); 172 173 /* 174 * Set color parameters for display 175 * 176 * param dp pointer to main s5p-dp structure 177 * param color_depth Video input Bit Per Color 178 * param color_space Colorimetric format of input video 179 * param dynamic_range VESA range or CEA range 180 * param coeff YCbCr Coefficients of input video 181 */ 182 void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, 183 unsigned int color_depth, 184 unsigned int color_space, 185 unsigned int dynamic_range, 186 unsigned int coeff); 187 /* 188 * Check whether video clock is on 189 * 190 * param dp pointer to main s5p-dp structure 191 * return clock status 192 */ 193 int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp); 194 /* 195 * Check whether video clock is on 196 * 197 * param dp pointer to main s5p-dp structure 198 * param type clock_recovery_m_value_type 199 * param m_value to calculate m_vid value 200 * param n_value to calculate n_vid value 201 */ 202 void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, 203 enum clock_recovery_m_value_type type, 204 unsigned int m_value, 205 unsigned int n_value); 206 /* 207 * Set DP to video slave mode thereby enabling video master 208 * 209 * param dp pointer to main s5p-dp structure 210 */ 211 void s5p_dp_enable_video_master(struct s5p_dp_device *dp); 212 /* 213 * Check whether video stream is on 214 * 215 * param dp pointer to main s5p-dp structure 216 * return video stream status 217 */ 218 int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp); 219 /* 220 * Configure DP in slave mode 221 * 222 * param dp pointer to main s5p-dp structure 223 * param video_info pointer to main video_info structure. 224 */ 225 void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, 226 struct video_info *video_info); 227 228 /* 229 * Wait unitl HW link training done 230 * 231 * param dp pointer to main s5p-dp structure 232 */ 233 void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); 234 235 /* startup and init */ 236 struct exynos5_fimd_panel; 237 void fb_init(unsigned long int fb_size, void *lcdbase, 238 struct exynos5_fimd_panel *pd); 239 int dp_controller_init(struct s5p_dp_device *dp_device); 240 int lcd_ctrl_init(unsigned long int fb_size, 241 struct exynos5_fimd_panel *panel_data, void *lcdbase); 242 #endif /* CPU_SAMSUNG_EXYNOS5250_DP_CORE_H */ 243