1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _TEGRA210_CLST_CLK_H_ 4 #define _TEGRA210_CLST_CLK_H_ 5 6 /* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */ 7 struct __packed clst_clk_ctlr { 8 u32 pllx_base; /* _PLLX_BASE, 0x000 */ 9 u32 pllx_misc; /* _PLLX_MISC, 0x004 */ 10 u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */ 11 u32 pllx_misc2; /* _PLLX_MISC_2, 0x00c */ 12 u32 pllx_misc3; /* _PLLX_MISC_3, 0x010 */ 13 u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x014 */ 14 u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x018 */ 15 u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x01c */ 16 u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ 17 u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ 18 u32 _rsv1[10]; /* 0x028-04c */ 19 u32 shaper; /* _SHAPER, 0x050 */ 20 u32 shaper1; /* _SHAPER_1, 0x054 */ 21 u32 _rsv2[80]; /* 0x058-194 */ 22 u32 misc_ctrl; /* _MISC_CTRL, 0x198 */ 23 }; 24 check_member(clst_clk_ctlr, misc_ctrl, 0x198); 25 26 /* CC_CCLK_BRST_POL */ 27 enum { 28 CC_CCLK_BRST_POL_PLLX_OUT0_LJ = 0x8, 29 }; 30 31 /* CC_SUPER_CCLK_DIVIDER */ 32 enum { 33 CC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 34 }; 35 36 /* PLLX_MISC3 */ 37 enum { 38 PLLX_IDDQ = 1 << 3, 39 }; 40 41 /* MISC_CTRL */ 42 enum { 43 CLK_SWITCH_MATCH = 1 << 5, 44 }; 45 46 #define CLK_SWITCH_TIMEOUT_US 1000 47 #endif /* _TEGRA210_CLST_CLK_H_ */ 48