1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* TODO: Update for Phoenix */ 4 5 #ifndef PHOENIX_CHIP_H 6 #define PHOENIX_CHIP_H 7 8 #include <amdblocks/chip.h> 9 #include <amdblocks/i2c.h> 10 #include <amdblocks/pci_clk_req.h> 11 #include <gpio.h> 12 #include <soc/i2c.h> 13 #include <soc/southbridge.h> 14 #include <drivers/i2c/designware/dw_i2c.h> 15 #include <types.h> 16 #if CONFIG(PLATFORM_USES_FSP2_0) 17 #include <vendorcode/amd/fsp/phoenix/FspUsb.h> 18 #else 19 #include "chip_opensil.h" 20 #endif 21 22 struct soc_amd_phoenix_config { 23 struct soc_amd_common_config common_config; 24 u8 i2c_scl_reset; 25 struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; 26 struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; 27 28 /* Enable S0iX support */ 29 bool s0ix_enable; 30 31 enum { 32 DOWNCORE_AUTO = 0, 33 DOWNCORE_1 = 1, /* Run with 1 physical core */ 34 DOWNCORE_2 = 3, /* Run with 2 physical cores */ 35 DOWNCORE_3 = 4, /* Run with 3 physical cores */ 36 DOWNCORE_4 = 6, /* Run with 4 physical cores */ 37 DOWNCORE_5 = 8, /* Run with 5 physical cores */ 38 DOWNCORE_6 = 9, /* Run with 6 physical cores */ 39 DOWNCORE_7 = 10, /* Run with 7 physical cores */ 40 } downcore_mode; 41 bool disable_smt; /* disable second thread on all physical cores */ 42 43 uint8_t stt_control; 44 uint8_t stt_pcb_sensor_count; 45 uint16_t stt_min_limit; 46 uint16_t stt_m1; 47 uint16_t stt_m2; 48 uint16_t stt_m3; 49 uint16_t stt_m4; 50 uint16_t stt_m5; 51 uint16_t stt_m6; 52 uint16_t stt_c_apu; 53 uint16_t stt_c_gpu; 54 uint16_t stt_c_hs2; 55 uint16_t stt_alpha_apu; 56 uint16_t stt_alpha_gpu; 57 uint16_t stt_alpha_hs2; 58 uint16_t stt_skin_temp_apu; 59 uint16_t stt_skin_temp_gpu; 60 uint16_t stt_skin_temp_hs2; 61 uint16_t stt_error_coeff; 62 uint16_t stt_error_rate_coefficient; 63 64 /* Default */ 65 uint8_t stapm_boost; 66 uint32_t stapm_time_constant_s; 67 uint32_t apu_only_sppt_limit; 68 uint32_t sustained_power_limit_mW; 69 uint32_t fast_ppt_limit_mW; 70 uint32_t slow_ppt_limit_mW; 71 uint32_t slow_ppt_time_constant_s; 72 uint32_t thermctl_limit_degreeC; 73 uint32_t vrm_current_limit_mA; 74 uint32_t vrm_maximum_current_limit_mA; 75 uint32_t vrm_soc_current_limit_mA; 76 /* Throttle (e.g., Low/No Battery) */ 77 uint32_t vrm_current_limit_throttle_mA; 78 uint32_t vrm_maximum_current_limit_throttle_mA; 79 uint32_t vrm_soc_current_limit_throttle_mA; 80 81 uint8_t smartshift_enable; 82 83 uint8_t system_configuration; 84 85 uint8_t cppc_ctrl; 86 uint8_t cppc_perf_limit_max_range; 87 uint8_t cppc_perf_limit_min_range; 88 uint8_t cppc_epp_max_range; 89 uint8_t cppc_epp_min_range; 90 uint8_t cppc_preferred_cores; 91 92 /* telemetry settings */ 93 uint32_t telemetry_vddcrvddfull_scale_current_mA; 94 uint32_t telemetry_vddcrvddoffset; 95 uint32_t telemetry_vddcrsocfull_scale_current_mA; 96 uint32_t telemetry_vddcrsocoffset; 97 98 /* The array index is the general purpose PCIe clock output number. Values in here 99 aren't the values written to the register to have the default to be always on. */ 100 enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; 101 102 /* performance policy for the PCIe links: power consumption vs. link speed */ 103 enum { 104 DXIO_PSPP_DISABLED = 0, 105 DXIO_PSPP_PERFORMANCE, 106 DXIO_PSPP_BALANCED, 107 DXIO_PSPP_POWERSAVE, 108 } pspp_policy; 109 110 uint8_t usb_phy_custom; 111 struct usb_phy_config usb_phy; 112 113 #if !CONFIG(PLATFORM_USES_FSP2_0) 114 struct ddi_descriptor ddi[DDI_DESCRIPTOR_COUNT]; 115 #endif 116 }; 117 118 #endif /* PHOENIX_CHIP_H */ 119