xref: /aosp_15_r20/external/coreboot/src/soc/amd/common/block/smbus/smbus_early_fch.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <stdint.h>
4 #include <amdblocks/acpimmio.h>
5 #include <amdblocks/smbus.h>
6 #include <soc/iomap.h>
7 
fch_smbus_enable_decode(uint16_t base)8 static void fch_smbus_enable_decode(uint16_t base)
9 {
10 	uint32_t val = pm_read32(PM_DECODE_EN);
11 	/* Configure upper byte of the I/O address; lower byte is always 0 */
12 	val = (val & ~SMBUS_ASF_IO_BASE_MASK) | (base & SMBUS_ASF_IO_BASE_MASK);
13 	/* Set enable decode bit even though it should already be set */
14 	val |= SMBUS_ASF_IO_EN;
15 	pm_write32(PM_DECODE_EN, val);
16 }
17 
fch_smbus_init(void)18 void fch_smbus_init(void)
19 {
20 	/* 400 kHz smbus speed. */
21 	const uint8_t smbus_speed = (66000000 / (400000 * 4));
22 
23 	fch_smbus_enable_decode(SMB_BASE_ADDR);
24 	smbus_write8(SMBTIMING, smbus_speed);
25 	/* Clear all SMBUS status bits */
26 	smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
27 	smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
28 	asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
29 	asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
30 }
31