1 /* -*- mesa-c++ -*- 2 * Copyright 2022 Collabora LTD 3 * Author: Gert Wollny <[email protected]> 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef GDSINSTR_H 8 #define GDSINSTR_H 9 10 #include "sfn_instr.h" 11 #include "sfn_valuefactory.h" 12 13 namespace r600 { 14 15 class Shader; 16 17 class GDSInstr : public Instr, public Resource { 18 public: 19 GDSInstr( 20 ESDOp op, Register *dest, const RegisterVec4& src, int uav_base, PRegister uav_id); 21 22 bool is_equal_to(const GDSInstr& lhs) const; 23 24 void accept(ConstInstrVisitor& visitor) const override; 25 void accept(InstrVisitor& visitor) override; 26 27 bool do_ready() const override; 28 opcode()29 auto opcode() const { return m_op; } src()30 auto& src() { return m_src; } src()31 auto& src() const { return m_src; } 32 dest()33 const auto& dest() const { return m_dest; } dest()34 auto& dest() { return m_dest; } 35 36 static auto from_string(std::istream& is, ValueFactory& value_factory) -> Pointer; 37 38 static bool emit_atomic_counter(nir_intrinsic_instr *intr, Shader& shader); slots()39 uint32_t slots() const override { return 1; }; 40 uint8_t allowed_src_chan_mask() const override; 41 42 void update_indirect_addr(PRegister old_reg, PRegister addr) override; 43 44 private: 45 static bool emit_atomic_read(nir_intrinsic_instr *intr, Shader& shader); 46 static bool emit_atomic_op2(nir_intrinsic_instr *intr, Shader& shader); 47 static bool emit_atomic_inc(nir_intrinsic_instr *intr, Shader& shader); 48 static bool emit_atomic_pre_dec(nir_intrinsic_instr *intr, Shader& shader); 49 50 void do_print(std::ostream& os) const override; 51 52 ESDOp m_op{DS_OP_INVALID}; 53 Register *m_dest; 54 55 RegisterVec4 m_src; 56 57 std::bitset<8> m_tex_flags; 58 }; 59 60 class RatInstr : public Instr, public Resource { 61 62 public: 63 enum ERatOp { 64 NOP, 65 STORE_TYPED, 66 STORE_RAW, 67 STORE_RAW_FDENORM, 68 CMPXCHG_INT, 69 CMPXCHG_FLT, 70 CMPXCHG_FDENORM, 71 ADD, 72 SUB, 73 RSUB, 74 MIN_INT, 75 MIN_UINT, 76 MAX_INT, 77 MAX_UINT, 78 AND, 79 OR, 80 XOR, 81 MSKOR, 82 INC_UINT, 83 DEC_UINT, 84 NOP_RTN = 32, 85 XCHG_RTN = 34, 86 XCHG_FDENORM_RTN, 87 CMPXCHG_INT_RTN, 88 CMPXCHG_FLT_RTN, 89 CMPXCHG_FDENORM_RTN, 90 ADD_RTN, 91 SUB_RTN, 92 RSUB_RTN, 93 MIN_INT_RTN, 94 MIN_UINT_RTN, 95 MAX_INT_RTN, 96 MAX_UINT_RTN, 97 AND_RTN, 98 OR_RTN, 99 XOR_RTN, 100 MSKOR_RTN, 101 UINT_RTN, 102 UNSUPPORTED 103 }; 104 105 RatInstr(ECFOpCode cf_opcode, 106 ERatOp rat_op, 107 const RegisterVec4& data, 108 const RegisterVec4& index, 109 int rat_id, 110 PRegister rat_id_offset, 111 int burst_count, 112 int comp_mask, 113 int element_size); 114 rat_op()115 ERatOp rat_op() const { return m_rat_op; } 116 value()117 const auto& value() const { return m_data; } value()118 auto& value() { return m_data; } 119 addr()120 const auto& addr() const { return m_index; } addr()121 auto& addr() { return m_index; } 122 data_gpr()123 int data_gpr() const { return m_data.sel(); } index_gpr()124 int index_gpr() const { return m_index.sel(); } elm_size()125 int elm_size() const { return m_element_size; } 126 comp_mask()127 int comp_mask() const { return m_comp_mask; } 128 need_ack()129 bool need_ack() const { return m_need_ack; } burst_count()130 int burst_count() const { return m_burst_count; } 131 data_swz(int chan)132 int data_swz(int chan) const { return m_data[chan]->chan(); } 133 cf_opcode()134 ECFOpCode cf_opcode() const { return m_cf_opcode; } 135 set_ack()136 void set_ack() 137 { 138 m_need_ack = true; 139 set_mark(); 140 } set_mark()141 void set_mark() { m_need_mark = true; } mark()142 bool mark() { return m_need_mark; } 143 144 void accept(ConstInstrVisitor& visitor) const override; 145 void accept(InstrVisitor& visitor) override; 146 147 bool is_equal_to(const RatInstr& lhs) const; 148 149 static bool emit(nir_intrinsic_instr *intr, Shader& shader); 150 151 void update_indirect_addr(PRegister old_reg, PRegister addr) override; 152 153 private: 154 static bool emit_global_store(nir_intrinsic_instr *intr, Shader& shader); 155 156 static bool emit_ssbo_load(nir_intrinsic_instr *intr, Shader& shader); 157 static bool emit_ssbo_store(nir_intrinsic_instr *intr, Shader& shader); 158 static bool emit_ssbo_atomic_op(nir_intrinsic_instr *intr, Shader& shader); 159 static bool emit_ssbo_size(nir_intrinsic_instr *intr, Shader& shader); 160 161 static bool emit_image_store(nir_intrinsic_instr *intr, Shader& shader); 162 static bool emit_image_load_or_atomic(nir_intrinsic_instr *intr, Shader& shader); 163 static bool emit_image_size(nir_intrinsic_instr *intr, Shader& shader); 164 static bool emit_image_samples(nir_intrinsic_instr *intrin, Shader& shader); 165 166 bool do_ready() const override; 167 void do_print(std::ostream& os) const override; 168 169 ECFOpCode m_cf_opcode; 170 ERatOp m_rat_op; 171 172 RegisterVec4 m_data; 173 RegisterVec4 m_index; 174 175 int m_burst_count{0}; 176 int m_comp_mask{15}; 177 int m_element_size{3}; 178 bool m_need_ack{false}; 179 bool m_need_mark{false}; 180 }; 181 182 } // namespace r600 183 184 #endif // GDSINSTR_H 185