1 /*
2 * Copyright (c) 2020 Qualcomm Technologies.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above
10 * copyright notice, this list of conditions and the following
11 * disclaimer in the documentation and/or other materials provided
12 * with the distribution.
13 * * Neither the name of The Linux Foundation nor the names of its
14 * contributors may be used to endorse or promote products derived
15 * from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /* For simplicity sake let's rely on coreboot initializing the UART. */
31 #include <config.h>
32 #include <libpayload.h>
33 #include <sys/types.h>
34
35 #define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK 0x1
36 #define RX_FIFO_WC_MSK 0x1FFFFFF
37 #define START_UART_TX 0x8000000
38
39 union proto_word_len {
40 u32 uart_tx_word_len;
41 u32 spi_word_len;
42 };
43
44 union proto_tx_trans_len {
45 u32 uart_tx_stop_bit_len;
46 u32 i2c_tx_trans_len;
47 u32 spi_tx_trans_len;
48 };
49
50 union proto_rx_trans_len {
51 u32 uart_tx_trans_len;
52 u32 i2c_rx_trans_len;
53 u32 spi_rx_trans_len;
54 };
55
56 struct qup_regs {
57 u32 geni_init_cfg_revision;
58 u32 geni_s_init_cfg_revision;
59 u8 _reserved1[0x10 - 0x08];
60 u32 geni_general_cfg;
61 u32 geni_rx_fifo_ctrl;
62 u8 _reserved2[0x20 - 0x18];
63 u32 geni_force_default_reg;
64 u32 geni_output_ctrl;
65 u32 geni_cgc_ctrl;
66 u32 geni_char_cfg;
67 u32 geni_char_data_n;
68 u8 _reserved3[0x40 - 0x34];
69 u32 geni_status;
70 u32 geni_test_bus_ctrl;
71 u32 geni_ser_m_clk_cfg;
72 u32 geni_ser_s_clk_cfg;
73 u32 geni_prog_rom_ctrl_reg;
74 u8 _reserved4[0x60 - 0x54];
75 u32 geni_clk_ctrl_ro;
76 u32 fifo_if_disable_ro;
77 u32 geni_fw_revision_ro;
78 u32 geni_s_fw_revision_ro;
79 u32 geni_fw_multilock_protns_ro;
80 u32 geni_fw_multilock_msa_ro;
81 u32 geni_fw_multilock_sp_ro;
82 u32 geni_clk_sel;
83 u32 geni_dfs_if_cfg;
84 u8 _reserved5[0x100 - 0x084];
85 u32 geni_cfg_reg0;
86 u32 geni_cfg_reg1;
87 u32 geni_cfg_reg2;
88 u32 geni_cfg_reg3;
89 u32 geni_cfg_reg4;
90 u32 geni_cfg_reg5;
91 u32 geni_cfg_reg6;
92 u32 geni_cfg_reg7;
93 u32 geni_cfg_reg8;
94 u32 geni_cfg_reg9;
95 u32 geni_cfg_reg10;
96 u32 geni_cfg_reg11;
97 u32 geni_cfg_reg12;
98 u32 geni_cfg_reg13;
99 u32 geni_cfg_reg14;
100 u32 geni_cfg_reg15;
101 u32 geni_cfg_reg16;
102 u32 geni_cfg_reg17;
103 u32 geni_cfg_reg18;
104 u8 _reserved6[0x200 - 0x14C];
105 u32 geni_cfg_reg64;
106 u32 geni_cfg_reg65;
107 u32 geni_cfg_reg66;
108 u32 geni_cfg_reg67;
109 u32 geni_cfg_reg68;
110 u32 geni_cfg_reg69;
111 u32 geni_cfg_reg70;
112 u32 geni_cfg_reg71;
113 u32 geni_cfg_reg72;
114 u32 spi_cpha;
115 u32 geni_cfg_reg74;
116 u32 proto_loopback_cfg;
117 u32 spi_cpol;
118 u32 i2c_noise_cancellation_ctl;
119 u32 i2c_monitor_ctl;
120 u32 geni_cfg_reg79;
121 u32 geni_cfg_reg80;
122 u32 geni_cfg_reg81;
123 u32 geni_cfg_reg82;
124 u32 spi_demux_output_inv;
125 u32 spi_demux_sel;
126 u32 geni_byte_granularity;
127 u32 geni_dma_mode_en;
128 u32 uart_tx_trans_cfg_reg;
129 u32 geni_tx_packing_cfg0;
130 u32 geni_tx_packing_cfg1;
131 union proto_word_len word_len;
132 union proto_tx_trans_len tx_trans_len;
133 union proto_rx_trans_len rx_trans_len;
134 u32 spi_pre_post_cmd_dly;
135 u32 i2c_scl_counters;
136 u32 geni_cfg_reg95;
137 u32 uart_rx_trans_cfg;
138 u32 geni_rx_packing_cfg0;
139 u32 geni_rx_packing_cfg1;
140 u32 uart_rx_word_len;
141 u32 geni_cfg_reg100;
142 u32 uart_rx_stale_cnt;
143 u32 geni_cfg_reg102;
144 u32 geni_cfg_reg103;
145 u32 geni_cfg_reg104;
146 u32 uart_tx_parity_cfg;
147 u32 uart_rx_parity_cfg;
148 u32 uart_manual_rfr;
149 u32 geni_cfg_reg108;
150 u32 geni_cfg_reg109;
151 u32 geni_cfg_reg110;
152 u8 _reserved7[0x600 - 0x2BC];
153 u32 geni_m_cmd0;
154 u32 geni_m_cmd_ctrl_reg;
155 u8 _reserved8[0x10 - 0x08];
156 u32 geni_m_irq_status;
157 u32 geni_m_irq_enable;
158 u32 geni_m_irq_clear;
159 u32 geni_m_irq_en_set;
160 u32 geni_m_irq_en_clear;
161 u32 geni_m_cmd_err_status;
162 u32 geni_m_fw_err_status;
163 u8 _reserved9[0x30 - 0x2C];
164 u32 geni_s_cmd0;
165 u32 geni_s_cmd_ctrl_reg;
166 u8 _reserved10[0x40 - 0x38];
167 u32 geni_s_irq_status;
168 u32 geni_s_irq_enable;
169 u32 geni_s_irq_clear;
170 u32 geni_s_irq_en_set;
171 u32 geni_s_irq_en_clear;
172 u8 _reserved11[0x700 - 0x654];
173 u32 geni_tx_fifon;
174 u8 _reserved12[0x780 - 0x704];
175 u32 geni_rx_fifon;
176 u8 _reserved13[0x800 - 0x784];
177 u32 geni_tx_fifo_status;
178 u32 geni_rx_fifo_status;
179 u32 geni_tx_fifo_threshold;
180 u32 geni_tx_watermark_reg;
181 u32 geni_rx_watermark_reg;
182 u32 geni_rx_rfr_watermark_reg;
183 u8 _reserved14[0x900 - 0x818];
184 u32 geni_gp_output_reg;
185 u8 _reserved15[0x908 - 0x904];
186 u32 geni_ios;
187 u32 geni_timestamp;
188 u32 geni_m_gp_length;
189 u32 geni_s_gp_length;
190 u8 _reserved16[0x920 - 0x918];
191 u32 geni_hw_irq_en;
192 u32 geni_hw_irq_ignore_on_active;
193 u8 _reserved17[0x930 - 0x928];
194 u32 geni_hw_irq_cmd_param_0;
195 u8 _reserved18[0xA00 - 0x934];
196 u32 geni_i3c_ibi_cfg_tablen;
197 u8 _reserved19[0xA80 - 0xA04];
198 u32 geni_i3c_ibi_status;
199 u32 geni_i3c_ibi_rd_data;
200 u32 geni_i3c_ibi_search_pattern;
201 u32 geni_i3c_ibi_search_data;
202 u32 geni_i3c_sw_ibi_en;
203 u32 geni_i3c_sw_ibi_en_recover;
204 u8 _reserved20[0xC30 - 0xA98];
205 u32 dma_tx_ptr_l;
206 u32 dma_tx_ptr_h;
207 u32 dma_tx_attr;
208 u32 dma_tx_length;
209 u32 dma_tx_irq_stat;
210 u32 dma_tx_irq_clr;
211 u32 dma_tx_irq_en;
212 u32 dma_tx_irq_en_set;
213 u32 dma_tx_irq_en_clr;
214 u32 dma_tx_length_in;
215 u32 dma_tx_fsm_rst;
216 u32 dma_tx_max_burst_size;
217 u8 _reserved21[0xD30 - 0xC60];
218 u32 dma_rx_ptr_l;
219 u32 dma_rx_ptr_h;
220 u32 dma_rx_attr;
221 u32 dma_rx_length;
222 u32 dma_rx_irq_stat;
223 u32 dma_rx_irq_clr;
224 u32 dma_rx_irq_en;
225 u32 dma_rx_irq_en_set;
226 u32 dma_rx_irq_en_clr;
227 u32 dma_rx_length_in;
228 u32 dma_rx_fsm_rst;
229 u32 dma_rx_max_burst_size;
230 u32 dma_rx_flush;
231 u8 _reserved22[0xE14 - 0xD64];
232 u32 se_irq_high_priority;
233 u32 se_gsi_event_en;
234 u32 se_irq_en;
235 u32 dma_if_en_ro;
236 u32 se_hw_param_0;
237 u32 se_hw_param_1;
238 u32 se_hw_param_2;
239 u32 dma_general_cfg;
240 u8 _reserved23[0x40 - 0x34];
241 u32 dma_debug_reg0;
242 u32 dma_test_bus_ctrl;
243 u32 se_top_test_bus_ctrl;
244 u8 _reserved24[0x1000 - 0x0E4C];
245 u32 se_geni_fw_revision;
246 u32 se_s_fw_revision;
247 u8 _reserved25[0x10-0x08];
248 u32 se_geni_cfg_ramn;
249 u8 _reserved26[0x2000 - 0x1014];
250 u32 se_geni_clk_ctrl;
251 u32 se_dma_if_en;
252 u32 se_fifo_if_disable;
253 u32 se_geni_fw_multilock_protns;
254 u32 se_geni_fw_multilock_msa;
255 u32 se_geni_fw_multilock_sp;
256 };
257 check_member(qup_regs, geni_clk_sel, 0x7C);
258 check_member(qup_regs, geni_cfg_reg108, 0x2B0);
259 check_member(qup_regs, geni_dma_mode_en, 0x258);
260 check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84);
261 check_member(qup_regs, dma_test_bus_ctrl, 0xE44);
262 check_member(qup_regs, se_geni_cfg_ramn, 0x1010);
263 check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014);
264
265 static struct console_input_driver consin = {
266 .havekey = serial_havechar,
267 .getchar = serial_getchar,
268 .input_type = CONSOLE_INPUT_TYPE_UART,
269 };
270
271 static struct console_output_driver consout = {
272 .putchar = serial_putchar,
273 };
274
uart_base_address(void)275 static struct qup_regs *uart_base_address(void)
276 {
277 const struct cb_serial *const serial = phys_to_virt(lib_sysinfo.cb_serial);
278 return phys_to_virt(serial->baseaddr);
279 }
280
uart_qupv3_tx_flush(void)281 static void uart_qupv3_tx_flush(void)
282 {
283 struct qup_regs *regs = uart_base_address();
284
285 while (read32(®s->geni_status) & GENI_STATUS_M_GENI_CMD_ACTIVE_MASK)
286 ;
287 }
288
uart_qupv3_rx_byte(void)289 static unsigned char uart_qupv3_rx_byte(void)
290 {
291 struct qup_regs *regs = uart_base_address();
292
293 if (read32(®s->geni_rx_fifo_status) & RX_FIFO_WC_MSK)
294 return read32(®s->geni_rx_fifon) & 0xFF;
295
296 return 0;
297 }
298
uart_qupv3_tx_byte(unsigned char data)299 static void uart_qupv3_tx_byte(unsigned char data)
300 {
301 struct qup_regs *regs = uart_base_address();
302
303 uart_qupv3_tx_flush();
304
305 write32(®s->rx_trans_len.uart_tx_trans_len, 1);
306 /* Start TX */
307 write32(®s->geni_m_cmd0, START_UART_TX);
308 write32(®s->geni_tx_fifon, data);
309 }
310
serial_putchar(unsigned int data)311 void serial_putchar(unsigned int data)
312 {
313 if (data == 0xa)
314 uart_qupv3_tx_byte(0xd);
315 uart_qupv3_tx_byte(data);
316 }
317
serial_havechar(void)318 int serial_havechar(void)
319 {
320 struct qup_regs *regs = uart_base_address();
321
322 if (read32(®s->geni_rx_fifo_status) & RX_FIFO_WC_MSK)
323 return 1;
324
325 return 0;
326 }
327
serial_getchar(void)328 int serial_getchar(void)
329 {
330 return uart_qupv3_rx_byte();
331 }
332
serial_console_init(void)333 void serial_console_init(void)
334 {
335 if (!lib_sysinfo.cb_serial)
336 return;
337
338 console_add_output_driver(&consout);
339 console_add_input_driver(&consin);
340 }
341