1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <cbfs.h>
4 #include <cf9_reset.h>
5 #include <option.h>
6 #include <cpu/x86/msr.h>
7 #include <console/console.h>
8 #include <cpu/intel/model_206ax/model_206ax.h>
9 #include <southbridge/intel/common/gpio.h>
10 #include <superio/smsc/sch5545/sch5545.h>
11 #include <superio/smsc/sch5545/sch5545_emi.h>
12
13 #include <baseboard/sch5545_ec.h>
14 #include <variant/sch5545_ec_tables.h>
15
16 #define GPIO_CHASSIS_ID0 1
17 #define GPIO_CHASSIS_ID1 17
18 #define GPIO_CHASSIS_ID2 37
19 #define GPIO_FRONT_PANEL_CHASSIS_DET_L 70
20
21 static const struct ec_val_reg ec_hwm_init_seq[] = {
22 { 0xa0, 0x02fc },
23 { 0x32, 0x02fd },
24 { 0x77, 0x0005 },
25 { 0x0f, 0x0018 },
26 { 0x2f, 0x0019 },
27 { 0x2f, 0x001a },
28 { 0x33, 0x008a },
29 { 0x33, 0x008b },
30 { 0x33, 0x008c },
31 { 0x10, 0x00ba },
32 { 0xff, 0x00d1 },
33 { 0xff, 0x00d6 },
34 { 0xff, 0x00db },
35 { 0x00, 0x0048 },
36 { 0x00, 0x0049 },
37 { 0x00, 0x007a },
38 { 0x00, 0x007b },
39 { 0x00, 0x007c },
40 { 0x00, 0x0080 },
41 { 0x00, 0x0081 },
42 { 0x00, 0x0082 },
43 { 0xbb, 0x0083 },
44 { 0xb0, 0x0084 },
45 { 0x88, 0x01a1 },
46 { 0x80, 0x01a4 },
47 { 0x00, 0x0088 },
48 { 0x00, 0x0089 },
49 { 0x02, 0x00a0 },
50 { 0x02, 0x00a1 },
51 { 0x02, 0x00a2 },
52 { 0x04, 0x00a4 },
53 { 0x04, 0x00a5 },
54 { 0x04, 0x00a6 },
55 { 0x00, 0x00ab },
56 { 0x3f, 0x00ad },
57 { 0x07, 0x00b7 },
58 { 0x50, 0x0062 },
59 { 0x46, 0x0063 },
60 { 0x50, 0x0064 },
61 { 0x46, 0x0065 },
62 { 0x50, 0x0066 },
63 { 0x46, 0x0067 },
64 { 0x98, 0x0057 },
65 { 0x98, 0x0059 },
66 { 0x7c, 0x0061 },
67 { 0x00, 0x01bc },
68 { 0x00, 0x01bd },
69 { 0x00, 0x01bb },
70 { 0xdd, 0x0085 },
71 { 0xdd, 0x0086 },
72 { 0x07, 0x0087 },
73 { 0x5e, 0x0090 },
74 { 0x5e, 0x0091 },
75 { 0x5d, 0x0095 },
76 { 0x00, 0x0096 },
77 { 0x00, 0x0097 },
78 { 0x00, 0x009b },
79 { 0x86, 0x00ae },
80 { 0x86, 0x00af },
81 { 0x67, 0x00b3 },
82 { 0xff, 0x00c4 },
83 { 0xff, 0x00c5 },
84 { 0xff, 0x00c9 },
85 { 0x01, 0x0040 },
86 { 0x00, 0x02fc },
87 { 0x9a, 0x02b3 },
88 { 0x05, 0x02b4 },
89 { 0x01, 0x02cc },
90 { 0x4c, 0x02d0 },
91 { 0x01, 0x02d2 },
92 { 0x01, 0x006f },
93 { 0x02, 0x0070 },
94 { 0x03, 0x0071 },
95 };
96
97
send_mbox_msg_with_int(uint8_t mbox_message)98 static uint8_t send_mbox_msg_with_int(uint8_t mbox_message)
99 {
100 uint8_t int_sts, int_cond;
101
102 sch5545_emi_h2ec_mbox_write(mbox_message);
103
104 do {
105 int_sts = sch5545_emi_get_int_src_low();
106 int_cond = int_sts & 0x71;
107 } while (int_cond == 0);
108
109 sch5545_emi_set_int_src_low(int_cond);
110
111 if ((int_sts & 1) == 0)
112 return 0;
113
114 if (sch5545_emi_ec2h_mbox_read() == mbox_message)
115 return 1;
116
117 return 0;
118 }
119
send_mbox_msg_simple(uint8_t mbox_message)120 static uint8_t send_mbox_msg_simple(uint8_t mbox_message)
121 {
122 uint8_t int_sts;
123
124 sch5545_emi_h2ec_mbox_write(mbox_message);
125
126 do {
127 int_sts = sch5545_emi_get_int_src_low();
128 if ((int_sts & 70) != 0)
129 return 0;
130 } while ((int_sts & 1) == 0);
131
132 if (sch5545_emi_ec2h_mbox_read() == mbox_message)
133 return 1;
134
135 return 0;
136 }
137
ec_check_mbox_and_int_status(uint8_t int_src,uint8_t mbox_msg)138 static void ec_check_mbox_and_int_status(uint8_t int_src, uint8_t mbox_msg)
139 {
140 uint8_t val;
141
142 val = sch5545_emi_ec2h_mbox_read();
143 if (val != mbox_msg)
144 printk(BIOS_SPEW, "EC2H mailbox should be %02x, is %02x\n", mbox_msg, val);
145
146 val = sch5545_emi_get_int_src_low();
147 if (val != int_src)
148 printk(BIOS_SPEW, "EC INT SRC should be %02x, is %02x\n", int_src, val);
149
150 sch5545_emi_set_int_src_low(val);
151 }
152
ec_read_write_reg(uint8_t ldn,uint16_t reg,uint8_t * value,uint8_t rw_bit)153 static uint8_t ec_read_write_reg(uint8_t ldn, uint16_t reg, uint8_t *value, uint8_t rw_bit)
154 {
155 uint8_t int_mask_bckup, ret = 0;
156 rw_bit &= 1;
157
158 int_mask_bckup = sch5545_emi_get_int_mask_low();
159 sch5545_emi_set_int_mask_low(0);
160
161 sch5545_emi_ec_write16(0x8000, (ldn << 1) | 0x100 | rw_bit);
162 if (rw_bit)
163 sch5545_emi_ec_write32(0x8004, (reg << 16) | *value);
164 else
165 sch5545_emi_ec_write32(0x8004, reg << 16);
166
167 ret = send_mbox_msg_with_int(1);
168 if (ret && !rw_bit)
169 *value = sch5545_emi_ec_read8(0x8004);
170 else if (ret != 1 && rw_bit)
171 printk(BIOS_WARNING, "EC mailbox returned unexpected value "
172 "when writing %02x to %04x\n", *value, reg);
173 else if (ret != 1 && !rw_bit)
174 printk(BIOS_WARNING, "EC mailbox returned unexpected value "
175 "when reading %04x\n", reg);
176
177 sch5545_emi_set_int_mask_low(int_mask_bckup);
178
179 return ret;
180 }
181
sch5545_get_ec_fw_version(void)182 uint16_t sch5545_get_ec_fw_version(void)
183 {
184 uint8_t val = 0;
185 uint16_t ec_fw_version;
186
187 /* Read the FW version currently loaded used by EC */
188 ec_read_write_reg(EC_HWM_LDN, 0x2ad, &val, READ_OP);
189 ec_fw_version = (val << 8);
190 ec_read_write_reg(EC_HWM_LDN, 0x2ae, &val, READ_OP);
191 ec_fw_version |= val;
192 ec_read_write_reg(EC_HWM_LDN, 0x2ac, &val, READ_OP);
193 ec_read_write_reg(EC_HWM_LDN, 0x2fd, &val, READ_OP);
194 ec_read_write_reg(EC_HWM_LDN, 0x2b0, &val, READ_OP);
195
196 return ec_fw_version;
197 }
198
sch5545_update_ec_firmware(uint16_t ec_version)199 void sch5545_update_ec_firmware(uint16_t ec_version)
200 {
201 uint8_t status;
202 uint16_t ec_fw_version;
203 uint32_t *ec_fw_file;
204 size_t ec_fw_file_size;
205
206 ec_fw_file = cbfs_map("sch5545_ecfw.bin", &ec_fw_file_size);
207
208 if (!ec_fw_file || ec_fw_file_size != 0x1750) {
209 printk(BIOS_ERR, "EC firmware file not found in CBFS!\n");
210 printk(BIOS_ERR, "The fans will keep running at maximum speed.\n");
211 return;
212 }
213
214 ec_fw_version = ec_fw_file[3] & 0xffff;
215
216 /*
217 * After power failure EC loses its configuration. The currently used firmware version
218 * by EC will be reported as 0x0000. In such case EC firmware needs to be uploaded.
219 */
220 if (ec_version != ec_fw_version) {
221 printk(BIOS_INFO, "SCH5545 EC is not functional, probably due to power "
222 "failure\n");
223 printk(BIOS_INFO, "Uploading EC firmware (version %04x) to SCH5545\n",
224 ec_fw_version);
225
226 if (!send_mbox_msg_simple(0x03)) {
227 printk(BIOS_WARNING, "EC didn't accept FW upload start signal\n");
228 printk(BIOS_WARNING, "EC firmware update failed!\n");
229 return;
230 }
231
232 sch5545_emi_ec_write32_bulk(0x8100, ec_fw_file, ec_fw_file_size);
233
234 status = send_mbox_msg_simple(0x04);
235 status += send_mbox_msg_simple(0x06);
236
237 if (status != 2)
238 printk(BIOS_WARNING, "EC firmware update failed!\n");
239
240 if (ec_fw_version != sch5545_get_ec_fw_version()) {
241 printk(BIOS_ERR, "EC firmware update failed!\n");
242 printk(BIOS_ERR, "The fans will keep running at maximum speed\n");
243 } else {
244 printk(BIOS_INFO, "EC firmware update success\n");
245 /*
246 * The vendor BIOS does a full reset after EC firmware update. Most
247 * likely because the fans are adapting very slowly after automatic fan
248 * control is enabled. This makes huge noise. To avoid it, also do the
249 * full reset. On next boot, it will not be necessary.
250 */
251 full_reset();
252 }
253 } else {
254 printk(BIOS_INFO, "SCH5545 EC firmware up to date (version %04x)\n",
255 ec_version);
256 }
257 }
258
sch5545_ec_hwm_early_init(void)259 void sch5545_ec_hwm_early_init(void)
260 {
261 uint8_t val = 0;
262 int i;
263
264 printk(BIOS_DEBUG, "%s\n", __func__);
265
266 ec_check_mbox_and_int_status(0x20, 0x01);
267
268 ec_read_write_reg(2, 0xcb, &val, READ_OP);
269 ec_read_write_reg(2, 0xb8, &val, READ_OP);
270
271 for (i = 0; i < ARRAY_SIZE(ec_hwm_init_seq); i++) {
272 val = ec_hwm_init_seq[i].val;
273 ec_read_write_reg(EC_HWM_LDN, ec_hwm_init_seq[i].reg, &val,
274 WRITE_OP);
275 }
276
277 ec_check_mbox_and_int_status(0x01, 0x01);
278 }
279
get_sku_tdp_config(void)280 static uint8_t get_sku_tdp_config(void)
281 {
282 msr_t msr;
283 uint32_t power_unit, tdp;
284 /* Get units */
285 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
286 power_unit = msr.lo & 0xf;
287
288 /* Get power defaults for this SKU */
289 msr = rdmsr(MSR_PKG_POWER_SKU);
290 tdp = msr.lo & 0x7fff;
291
292 /* These numbers will determine which settings to use to init EC */
293 if ((tdp >> power_unit) < 66)
294 return 16;
295 else
296 return 32;
297 }
298
get_chassis_type(void)299 static uint8_t get_chassis_type(void)
300 {
301 uint8_t chassis_id;
302
303 chassis_id = get_gpio(GPIO_CHASSIS_ID0);
304 chassis_id |= get_gpio(GPIO_CHASSIS_ID1) << 1;
305 chassis_id |= get_gpio(GPIO_CHASSIS_ID2) << 2;
306 chassis_id |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
307
308 /* This mapping will determine which EC init sequence to use */
309 switch (chassis_id) {
310 case 0x0:
311 case 0x4:
312 return 5; /* MT */
313 case 0x8:
314 return 4; /* DT */
315 case 0x3:
316 case 0xb:
317 return 3; /* USFF */
318 case 0x1:
319 case 0x9:
320 case 0x5:
321 case 0xd:
322 return 6; /* SFF */
323 default:
324 printk(BIOS_DEBUG, "Unknown chassis ID %x\n", chassis_id);
325 break;
326 }
327
328 return 0xff;
329 }
330
ec_hwm_init_late(const ec_chassis_tdp_t * ec_hwm_sequence,size_t size)331 static void ec_hwm_init_late(const ec_chassis_tdp_t *ec_hwm_sequence, size_t size)
332 {
333 unsigned int i;
334 uint8_t val;
335 uint8_t tdp_config = get_sku_tdp_config();
336
337 for (i = 0; i < size; i++) {
338 if (ec_hwm_sequence[i].tdp == tdp_config ||
339 ec_hwm_sequence[i].tdp == TDP_COMMON) {
340 val = ec_hwm_sequence[i].val;
341 ec_read_write_reg(EC_HWM_LDN, ec_hwm_sequence[i].reg, &val, WRITE_OP);
342 }
343 }
344 }
345
prepare_for_hwm_ec_sequence(uint8_t write_only,uint8_t * value)346 static void prepare_for_hwm_ec_sequence(uint8_t write_only, uint8_t *value)
347 {
348 uint16_t reg;
349 uint8_t val;
350
351 if (write_only == 1) {
352 val = *value;
353 reg = 0x02fc;
354 } else {
355 if (value != NULL)
356 ec_read_write_reg(EC_HWM_LDN, 0x02fc, value, READ_OP);
357 val = 0xa0;
358 ec_read_write_reg(EC_HWM_LDN, 0x2fc, &val, WRITE_OP);
359 val = 0x32;
360 reg = 0x02fd;
361 }
362
363 ec_read_write_reg(1, reg, &val, WRITE_OP);
364 }
365
sch5545_ec_hwm_init(void * unused)366 void sch5545_ec_hwm_init(void *unused)
367 {
368 uint8_t val = 0, val_2fc, chassis_type;
369
370 printk(BIOS_DEBUG, "%s\n", __func__);
371 sch5545_emi_init(0x2e);
372
373 chassis_type = get_chassis_type();
374
375 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
376 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
377 ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP);
378 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
379 val |= 0x02;
380 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
381
382 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
383 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
384 ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP);
385 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
386 val |= 0x04;
387 ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
388
389 ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP);
390 ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP);
391
392 ec_check_mbox_and_int_status(0x00, 0x01);
393
394 prepare_for_hwm_ec_sequence(0, &val_2fc);
395
396 if (chassis_type != 0xff) {
397 printk(BIOS_DEBUG, "Performing HWM init for chassis %d\n", chassis_type);
398 switch (chassis_type) {
399 case 3:
400 ec_hwm_init_late(ec_hwm_chassis3, ARRAY_SIZE(ec_hwm_chassis3));
401 break;
402 case 4:
403 ec_hwm_init_late(ec_hwm_chassis4, ARRAY_SIZE(ec_hwm_chassis4));
404 break;
405 case 5:
406 ec_hwm_init_late(ec_hwm_chassis5, ARRAY_SIZE(ec_hwm_chassis5));
407 break;
408 case 6:
409 ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis6));
410 break;
411 }
412 }
413
414 if (CONFIG_MAX_CPUS > 2) {
415 val = 0x30;
416 ec_read_write_reg(EC_HWM_LDN, 0x009e, &val, WRITE_OP);
417 ec_read_write_reg(EC_HWM_LDN, 0x00ea, &val, READ_OP);
418 ec_read_write_reg(EC_HWM_LDN, 0x00eb, &val, WRITE_OP);
419 }
420
421 ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP);
422
423 unsigned int fan_speed_full = get_uint_option("fan_full_speed", 0);
424 if (fan_speed_full) {
425 printk(BIOS_INFO, "Will set up fans to run at full speed\n");
426 ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP);
427 val |= 0x60;
428 ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, WRITE_OP);
429 ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP);
430 val |= 0x60;
431 ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, WRITE_OP);
432 } else {
433 printk(BIOS_INFO, "Will set up fans for automatic control\n");
434 }
435
436 ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP);
437
438
439 if (chassis_type == 4 || chassis_type == 5) {
440 ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP);
441 if (val == 0) {
442 printk(BIOS_INFO, "Applying HWM fix-up for MT/DT chassis\n");
443 ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, READ_OP);
444 val &= 0xfb;
445 ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, WRITE_OP);
446 ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, READ_OP);
447 val &= 0xfb;
448 ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, WRITE_OP);
449 ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, READ_OP);
450 val &= 0xfb;
451 ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, WRITE_OP);
452 val = 0x99;
453 ec_read_write_reg(EC_HWM_LDN, 0x008a, &val, WRITE_OP);
454 val = 0x47;
455 ec_read_write_reg(EC_HWM_LDN, 0x008b, &val, WRITE_OP);
456 val = 0x91;
457 ec_read_write_reg(EC_HWM_LDN, 0x008c, &val, WRITE_OP);
458 }
459 }
460
461 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP);
462 val &= 0xf7;
463 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP);
464
465 val = 0x6a;
466 if (chassis_type != 3)
467 ec_read_write_reg(EC_HWM_LDN, 0x0059, &val, WRITE_OP);
468 else
469 ec_read_write_reg(EC_HWM_LDN, 0x0057, &val, WRITE_OP);
470
471 ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, READ_OP);
472 val |= 0x40;
473 ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, WRITE_OP);
474
475 if (chassis_type == 3) {
476 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP);
477 val |= 0x04;
478 } else {
479 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP);
480 val |= 0x08;
481 }
482 ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP);
483
484 val = 0x0e;
485 ec_read_write_reg(EC_HWM_LDN, 0x007b, &val, WRITE_OP);
486 ec_read_write_reg(EC_HWM_LDN, 0x007c, &val, WRITE_OP);
487 val = 0x01;
488 ec_read_write_reg(EC_HWM_LDN, 0x007a, &val, WRITE_OP);
489 }
490