1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/ {
13	aliases {
14		i2c0 = &i2c0;
15		serial3 = &scif0;
16		mmc1 = &sdhi1;
17	};
18
19	chosen {
20		bootargs = "ignore_loglevel";
21		stdout-path = "serial3:115200n8";
22	};
23
24	keys {
25		compatible = "gpio-keys";
26
27		key-1 {
28			interrupts-extended = <&pinctrl RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
29			linux,code = <KEY_1>;
30			label = "USER_SW1";
31			wakeup-source;
32			debounce-interval = <20>;
33		};
34
35		key-2 {
36			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>;
37			linux,code = <KEY_2>;
38			label = "USER_SW2";
39			wakeup-source;
40			debounce-interval = <20>;
41		};
42
43		key-3 {
44			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
45			linux,code = <KEY_3>;
46			label = "USER_SW3";
47			wakeup-source;
48			debounce-interval = <20>;
49		};
50	};
51
52	snd_rzg3s: sound {
53		compatible = "simple-audio-card";
54		simple-audio-card,format = "i2s";
55		simple-audio-card,bitclock-master = <&cpu_dai>;
56		simple-audio-card,frame-master = <&cpu_dai>;
57		simple-audio-card,mclk-fs = <256>;
58
59		cpu_dai: simple-audio-card,cpu {
60			sound-dai = <&ssi3>;
61		};
62
63		codec_dai: simple-audio-card,codec {
64			sound-dai = <&da7212>;
65			clocks = <&versa3 1>;
66		};
67	};
68
69	vcc_sdhi1: regulator-vcc-sdhi1 {
70		compatible = "regulator-fixed";
71		regulator-name = "SDHI1 Vcc";
72		regulator-min-microvolt = <3300000>;
73		regulator-max-microvolt = <3300000>;
74		gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
75		enable-active-high;
76	};
77
78	vccq_sdhi1: regulator-vccq-sdhi1 {
79		compatible = "regulator-gpio";
80		regulator-name = "SDHI1 VccQ";
81		regulator-min-microvolt = <1800000>;
82		regulator-max-microvolt = <3300000>;
83		gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>;
84		gpios-states = <1>;
85		states = <3300000 1>, <1800000 0>;
86	};
87};
88
89&audio_clk2 {
90	clock-frequency = <12288000>;
91};
92
93&i2c0 {
94	status = "okay";
95
96	clock-frequency = <1000000>;
97
98	da7212: codec@1a {
99		compatible = "dlg,da7212";
100		reg = <0x1a>;
101
102		clocks = <&versa3 1>;
103		clock-names = "mclk";
104
105		#sound-dai-cells = <0>;
106
107		dlg,micbias1-lvl = <2500>;
108		dlg,micbias2-lvl = <2500>;
109		dlg,dmic-data-sel = "lrise_rfall";
110		dlg,dmic-samplephase = "between_clkedge";
111		dlg,dmic-clkrate = <3000000>;
112
113		VDDA-supply = <&reg_1p8v>;
114		VDDSP-supply = <&reg_3p3v>;
115		VDDMIC-supply = <&reg_3p3v>;
116		VDDIO-supply = <&reg_1p8v>;
117	};
118};
119
120&i2c1 {
121	status = "okay";
122
123	clock-frequency = <400000>;
124
125	power-monitor@44 {
126		compatible = "renesas,isl28022";
127		reg = <0x44>;
128		shunt-resistor-micro-ohms = <8000>;
129		renesas,average-samples = <32>;
130	};
131};
132
133&pinctrl {
134	audio_clock_pins: audio-clock {
135		pins = "AUDIO_CLK1", "AUDIO_CLK2";
136		input-enable;
137	};
138
139	key-1-gpio-hog {
140		gpio-hog;
141		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
142		input;
143		line-name = "key-1-gpio-irq";
144	};
145
146	key-2-gpio-hog {
147		gpio-hog;
148		gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
149		input;
150		line-name = "key-2-gpio-irq";
151	};
152
153	key-3-gpio-hog {
154		gpio-hog;
155		gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
156		input;
157		line-name = "key-3-gpio-irq";
158	};
159
160	scif0_pins: scif0 {
161		pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
162			 <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
163	};
164
165	sdhi1_pins: sd1 {
166		data {
167			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
168			power-source = <3300>;
169		};
170
171		ctrl {
172			pins = "SD1_CLK", "SD1_CMD";
173			power-source = <3300>;
174		};
175
176		cd {
177			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
178		};
179	};
180
181	sdhi1_pins_uhs: sd1-uhs {
182		data {
183			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
184			power-source = <1800>;
185		};
186
187		ctrl {
188			pins = "SD1_CLK", "SD1_CMD";
189			power-source = <1800>;
190		};
191
192		cd {
193			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
194		};
195	};
196
197	ssi3_pins: ssi3 {
198		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
199			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
200			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
201			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
202	};
203};
204
205&scif0 {
206	pinctrl-names = "default";
207	pinctrl-0 = <&scif0_pins>;
208	status = "okay";
209};
210
211&sdhi1 {
212	pinctrl-0 = <&sdhi1_pins>;
213	pinctrl-1 = <&sdhi1_pins_uhs>;
214	pinctrl-names = "default", "state_uhs";
215	vmmc-supply = <&vcc_sdhi1>;
216	vqmmc-supply = <&vccq_sdhi1>;
217	bus-width = <4>;
218	sd-uhs-sdr50;
219	sd-uhs-sdr104;
220	max-frequency = <125000000>;
221	status = "okay";
222};
223
224&ssi3 {
225	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
226		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
227		 <&versa3 2>, <&audio_clk2>;
228	pinctrl-names = "default";
229	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
230	status = "okay";
231};
232