1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _csi_rx_defs_h 8 #define _csi_rx_defs_h 9 10 //#include "rx_csi_common_defs.h" 11 12 #define MIPI_PKT_DATA_WIDTH 32 13 //#define CLK_CROSSING_FIFO_DEPTH 16 14 #define _CSI_RX_REG_ALIGN 4 15 16 //define number of IRQ (see below for definition of each IRQ bits) 17 #define CSI_RX_NOF_IRQS_BYTE_DOMAIN 11 18 #define CSI_RX_NOF_IRQS_ISP_DOMAIN 15 // CSI_RX_NOF_IRQS_BYTE_DOMAIN + remaining from Dphy_rx already on ISP clock domain 19 20 // REGISTER DESCRIPTION 21 //#define _HRT_CSI_RX_SOFTRESET_REG_IDX 0 22 #define _HRT_CSI_RX_ENABLE_REG_IDX 0 23 #define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1 24 #define _HRT_CSI_RX_ERROR_HANDLING_REG_IDX 2 25 #define _HRT_CSI_RX_STATUS_REG_IDX 3 26 #define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4 27 #define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5 28 //#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6 29 #define _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX 6 30 #define _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX 7 31 #define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx)) 32 #define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx) + 1) 33 34 #define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8 + 2 * (nof_dlanes)) 35 36 //#define _HRT_CSI_RX_SOFTRESET_REG_WIDTH 1 37 #define _HRT_CSI_RX_ENABLE_REG_WIDTH 1 38 #define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_WIDTH 3 39 #define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4 40 #define _HRT_CSI_RX_STATUS_REG_WIDTH 1 41 #define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8 42 #define _HRT_CSI_RX_STATUS_DLANE_LP_REG_WIDTH 24 43 #define _HRT_CSI_RX_IRQ_CONFIG_REG_WIDTH (CSI_RX_NOF_IRQS_ISP_DOMAIN) 44 #define _HRT_CSI_RX_DLY_CNT_REG_WIDTH 24 45 //#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS 46 //#define _HRT_CSI_RX_IRQ_CLEAR_REG_WIDTH 0 47 48 #define ONE_LANE_ENABLED 0 49 #define TWO_LANES_ENABLED 1 50 #define THREE_LANES_ENABLED 2 51 #define FOUR_LANES_ENABLED 3 52 53 // Error handling reg bit positions 54 #define ERR_DECISION_BIT 0 55 #define DISC_RESERVED_SP_BIT 1 56 #define DISC_RESERVED_LP_BIT 2 57 #define DIS_INCOMP_PKT_CHK_BIT 3 58 59 #define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_POSEDGE 0 60 #define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_ORIGINAL 1 61 62 // Interrupt bits 63 #define _HRT_RX_CSI_IRQ_SINGLE_PH_ERROR_CORRECTED 0 64 #define _HRT_RX_CSI_IRQ_MULTIPLE_PH_ERROR_DETECTED 1 65 #define _HRT_RX_CSI_IRQ_PAYLOAD_CHECKSUM_ERROR 2 66 #define _HRT_RX_CSI_IRQ_FIFO_FULL_ERROR 3 67 #define _HRT_RX_CSI_IRQ_RESERVED_SP_DETECTED 4 68 #define _HRT_RX_CSI_IRQ_RESERVED_LP_DETECTED 5 69 //#define _HRT_RX_CSI_IRQ_PREMATURE_SOP 6 70 #define _HRT_RX_CSI_IRQ_INCOMPLETE_PACKET 6 71 #define _HRT_RX_CSI_IRQ_FRAME_SYNC_ERROR 7 72 #define _HRT_RX_CSI_IRQ_LINE_SYNC_ERROR 8 73 #define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_ERROR 9 74 #define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_SYNC_ERROR 10 75 76 #define _HRT_RX_CSI_IRQ_DLANE_ESC_ERROR 11 77 #define _HRT_RX_CSI_IRQ_DLANE_TRIGGERESC 12 78 #define _HRT_RX_CSI_IRQ_DLANE_ULPSESC 13 79 #define _HRT_RX_CSI_IRQ_CLANE_ULPSCLKNOT 14 80 81 /* OLD ARASAN FRONTEND IRQs 82 #define _HRT_RX_CSI_IRQ_OVERRUN_BIT 0 83 #define _HRT_RX_CSI_IRQ_RESERVED_BIT 1 84 #define _HRT_RX_CSI_IRQ_SLEEP_MODE_ENTRY_BIT 2 85 #define _HRT_RX_CSI_IRQ_SLEEP_MODE_EXIT_BIT 3 86 #define _HRT_RX_CSI_IRQ_ERR_SOT_HS_BIT 4 87 #define _HRT_RX_CSI_IRQ_ERR_SOT_SYNC_HS_BIT 5 88 #define _HRT_RX_CSI_IRQ_ERR_CONTROL_BIT 6 89 #define _HRT_RX_CSI_IRQ_ERR_ECC_DOUBLE_BIT 7 90 #define _HRT_RX_CSI_IRQ_ERR_ECC_CORRECTED_BIT 8 91 #define _HRT_RX_CSI_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 92 #define _HRT_RX_CSI_IRQ_ERR_CRC_BIT 10 93 #define _HRT_RX_CSI_IRQ_ERR_ID_BIT 11 94 #define _HRT_RX_CSI_IRQ_ERR_FRAME_SYNC_BIT 12 95 #define _HRT_RX_CSI_IRQ_ERR_FRAME_DATA_BIT 13 96 #define _HRT_RX_CSI_IRQ_DATA_TIMEOUT_BIT 14 97 #define _HRT_RX_CSI_IRQ_ERR_ESCAPE_BIT 15 98 #define _HRT_RX_CSI_IRQ_ERR_LINE_SYNC_BIT 16 99 */ 100 101 ////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 102 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE0 0 103 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE1 1 104 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE2 2 105 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE3 3 106 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE0 4 107 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE1 5 108 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE2 6 109 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE3 7 110 111 ////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 112 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE0 0 113 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE1 1 114 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE2 2 115 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE3 3 116 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE0 4 117 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE0 5 118 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE0 6 119 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE0 7 120 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE1 8 121 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE1 9 122 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE1 10 123 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE1 11 124 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE2 12 125 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE2 13 126 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE2 14 127 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE2 15 128 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE3 16 129 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE3 17 130 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE3 18 131 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE3 19 132 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE0 20 133 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE1 21 134 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE2 22 135 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE3 23 136 137 /*********************************************************/ 138 /*** Relevant declarations from rx_csi_common_defs.h *****/ 139 /*********************************************************/ 140 /* packet bit definition */ 141 #define _HRT_RX_CSI_PKT_SOP_BITPOS 32 142 #define _HRT_RX_CSI_PKT_EOP_BITPOS 33 143 #define _HRT_RX_CSI_PKT_PAYLOAD_BITPOS 0 144 #define _HRT_RX_CSI_PH_CH_ID_BITPOS 22 145 #define _HRT_RX_CSI_PH_FMT_ID_BITPOS 16 146 #define _HRT_RX_CSI_PH_DATA_FIELD_BITPOS 0 147 148 #define _HRT_RX_CSI_PKT_SOP_BITS 1 149 #define _HRT_RX_CSI_PKT_EOP_BITS 1 150 #define _HRT_RX_CSI_PKT_PAYLOAD_BITS 32 151 #define _HRT_RX_CSI_PH_CH_ID_BITS 2 152 #define _HRT_RX_CSI_PH_FMT_ID_BITS 6 153 #define _HRT_RX_CSI_PH_DATA_FIELD_BITS 16 154 155 /* Definition of data format ID at the interface CSS_receiver units */ 156 #define _HRT_RX_CSI_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ 157 #define _HRT_RX_CSI_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ 158 #define _HRT_RX_CSI_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ 159 #define _HRT_RX_CSI_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ 160 161 #endif /* _csi_rx_defs_h */ 162