xref: /aosp_15_r20/external/coreboot/src/drivers/ricoh/rce822/rce822.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <device/pci_ops.h>
7 #include "chip.h"
8 
rce822_enable(struct device * dev)9 static void rce822_enable(struct device *dev)
10 {
11 	struct drivers_ricoh_rce822_config *config = dev->chip_info;
12 
13 	pci_write_config8(dev, 0xca, 0x57);
14 	pci_write_config8(dev, 0xcb, config->disable_mask);
15 	pci_write_config8(dev, 0xca, 0x00);
16 }
17 
rce822_init(struct device * dev)18 static void rce822_init(struct device *dev)
19 {
20 	struct drivers_ricoh_rce822_config *config = dev->chip_info;
21 
22 	pci_write_config8(dev, 0xf9, 0xfc);
23 	pci_write_config8(dev, 0xfb, config->sdwppol << 1);
24 	pci_write_config8(dev, 0xf9, 0x00);
25 }
26 
rce822_set_subsystem(struct device * dev,unsigned int vendor,unsigned int device)27 static void rce822_set_subsystem(struct device *dev, unsigned int vendor,
28 				 unsigned int device)
29 {
30 	if (!vendor || !device) {
31 		pci_write_config32(dev, 0xac,
32 				pci_read_config32(dev, PCI_VENDOR_ID));
33 	} else {
34 		pci_write_config32(dev, 0xac,
35 				((device & 0xffff) << 16) | (vendor & 0xffff));
36 	}
37 }
38 
39 static struct pci_operations lops_pci = {
40 	.set_subsystem	= rce822_set_subsystem,
41 };
42 
43 static struct device_operations rce822_ops = {
44 	.read_resources		= pci_dev_read_resources,
45 	.set_resources		= pci_dev_set_resources,
46 	.enable_resources	= pci_dev_enable_resources,
47 	.init			= rce822_init,
48 	.enable			= rce822_enable,
49 	.ops_pci		= &lops_pci,
50 };
51 
52 static const unsigned short pci_device_ids[] = { 0xe822, 0xe823, 0 };
53 
54 static const struct pci_driver rce822 __pci_driver = {
55 	.ops	 = &rce822_ops,
56 	.vendor	 = PCI_VID_RICOH,
57 	.devices = pci_device_ids,
58 };
59 
60 struct chip_operations drivers_ricoh_rce822_ops = {
61 	.name = "RICOH RCE822",
62 };
63