1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <types.h>
6
7 #include "sandybridge.h"
8
9 static const char *const ecc_decoder[] = {
10 "inactive",
11 "active on IO",
12 "disabled on IO",
13 "active",
14 };
15
16 #define ON_OFF(val) (((val) & 1) ? "on" : "off")
17
18 /* Print the memory controller configuration as read from the memory controller registers. */
report_memory_config(void)19 void report_memory_config(void)
20 {
21 u32 addr_decoder_common, addr_decode_ch[2];
22 int i;
23
24 addr_decoder_common = mchbar_read32(MAD_CHNL);
25 addr_decode_ch[0] = mchbar_read32(MAD_DIMM_CH0);
26 addr_decode_ch[1] = mchbar_read32(MAD_DIMM_CH1);
27
28 const int refclk = mchbar_read32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
29
30 printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
31 printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
32 DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * refclk * 100 * 2, 100));
33
34 printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
35 (addr_decoder_common >> 0) & 3,
36 (addr_decoder_common >> 2) & 3,
37 (addr_decoder_common >> 4) & 3);
38
39 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
40 u32 ch_conf = addr_decode_ch[i];
41 printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
42 printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
43 printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22));
44 printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21));
45 printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
46 ((ch_conf >> 0) & 0xff) * 256,
47 ((ch_conf >> 19) & 1) ? 16 : 8,
48 ((ch_conf >> 17) & 1) ? "dual" : "single",
49 ((ch_conf >> 16) & 1) ? "" : ", selected");
50 printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
51 ((ch_conf >> 8) & 0xff) * 256,
52 ((ch_conf >> 20) & 1) ? 16 : 8,
53 ((ch_conf >> 18) & 1) ? "dual" : "single",
54 ((ch_conf >> 16) & 1) ? ", selected" : "");
55 }
56 }
57 #undef ON_OFF
58