1 /**************************************************************************
2 *
3 * Copyright 2024 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8 #include "pipe/p_video_codec.h"
9
10 #include "util/u_video.h"
11
12 #include "si_pipe.h"
13 #include "radeon_vcn_enc.h"
14
15 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
16 #define RENCODE_FW_INTERFACE_MINOR_VERSION 3
17
18 #define RENCODE_REC_SWIZZLE_MODE_256B_D_VCN5 1
19
20 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
21 #define RENCODE_IB_PARAM_METADATA_BUFFER 0x0000001c
22 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER_OVERRIDE 0x0000001d
23 #define RENCODE_IB_PARAM_HEVC_ENCODE_PARAMS 0x00100004
24
25 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_END RENCODE_HEADER_INSTRUCTION_END
26 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY RENCODE_HEADER_INSTRUCTION_COPY
27 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV 0x00000005
28 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS 0x00000006
29 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER 0x00000007
30 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS 0x00000008
31 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID 0x00000009
32 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX 0x0000000a
33 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS 0x0000000b
34 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS 0x0000000c
35 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE 0x0000000d
36 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU 0x0000000e
37
38 #define RENCODE_AV1_IB_PARAM_TILE_CONFIG 0x00300002
39 #define RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION 0x00300003
40 #define RENCODE_IB_PARAM_AV1_ENCODE_PARAMS 0x00300004
41
42 #define RENCODE_AV1_MIN_TILE_WIDTH 256
43
radeon_enc_cdf_default_table(struct radeon_encoder * enc)44 static void radeon_enc_cdf_default_table(struct radeon_encoder *enc)
45 {
46 bool use_cdf_default = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
47 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY ||
48 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH ||
49 (enc->enc_pic.enable_error_resilient_mode);
50
51 enc->enc_pic.av1_cdf_default_table.use_cdf_default = use_cdf_default ? 1 : 0;
52
53 RADEON_ENC_BEGIN(enc->cmd.cdf_default_table_av1);
54 RADEON_ENC_CS(enc->enc_pic.av1_cdf_default_table.use_cdf_default);
55 RADEON_ENC_READWRITE(enc->cdf->res->buf, enc->cdf->res->domains, 0);
56 RADEON_ENC_END();
57 }
58
radeon_enc_spec_misc(struct radeon_encoder * enc)59 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
60 {
61 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
62 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
63 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
64 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
65 RADEON_ENC_CS(enc->enc_pic.spec_misc.transform_8x8_mode);
66 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
67 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
68 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
69 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
70 RADEON_ENC_CS(enc->enc_pic.spec_misc.b_picture_enabled);
71 RADEON_ENC_CS(enc->enc_pic.spec_misc.weighted_bipred_idc);
72 RADEON_ENC_END();
73 }
74
radeon_enc_encode_params(struct radeon_encoder * enc)75 static void radeon_enc_encode_params(struct radeon_encoder *enc)
76 {
77
78 bool is_av1 = u_reduce_video_profile(enc->base.profile)
79 == PIPE_VIDEO_FORMAT_AV1;
80 if ( !is_av1 ) {
81 switch (enc->enc_pic.picture_type) {
82 case PIPE_H2645_ENC_PICTURE_TYPE_I:
83 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
84 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
85 break;
86 case PIPE_H2645_ENC_PICTURE_TYPE_P:
87 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
88 break;
89 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
90 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
91 break;
92 case PIPE_H2645_ENC_PICTURE_TYPE_B:
93 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
94 break;
95 default:
96 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
97 }
98 } else {
99 switch (enc->enc_pic.frame_type) {
100 case PIPE_AV1_ENC_FRAME_TYPE_KEY:
101 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
102 break;
103 case PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY:
104 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
105 break;
106 case PIPE_AV1_ENC_FRAME_TYPE_INTER:
107 case PIPE_AV1_ENC_FRAME_TYPE_SWITCH:
108 case PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING:
109 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
110 break;
111 default:
112 assert(0); /* never come to this condition */
113 }
114 }
115
116 if (enc->luma->meta_offset) {
117 RVID_ERR("DCC surfaces not supported.\n");
118 assert(false);
119 }
120
121 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
122 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
123 enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;
124 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
125
126 RADEON_ENC_BEGIN(enc->cmd.enc_params);
127 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
128 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
129 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
130 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma ?
131 enc->chroma->u.gfx9.surf_offset : enc->luma->u.gfx9.surf_pitch);
132 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
133 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
134 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
135 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
136 RADEON_ENC_END();
137 }
138
radeon_enc_encode_params_h264(struct radeon_encoder * enc)139 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
140 {
141 if (enc->enc_pic.enc_params.reference_picture_index != 0xFFFFFFFF){
142 enc->enc_pic.h264_enc_params.lsm_reference_pictures[0].list = 0;
143 enc->enc_pic.h264_enc_params.lsm_reference_pictures[0].list_index = 0;
144 enc->enc_pic.h264_enc_params.ref_list0[0] =
145 enc->enc_pic.enc_params.reference_picture_index;
146 enc->enc_pic.h264_enc_params.num_active_references_l0 = 1;
147 } else {
148 enc->enc_pic.h264_enc_params.lsm_reference_pictures[0].list = 0;
149 enc->enc_pic.h264_enc_params.lsm_reference_pictures[0].list_index = 0xFFFFFFFF;
150 enc->enc_pic.h264_enc_params.ref_list0[0] = 0xFFFFFFFF;
151 enc->enc_pic.h264_enc_params.num_active_references_l0 = 0;
152 }
153
154 if (enc->enc_pic.h264_enc_params.l1_reference_picture0_index != 0xFFFFFFFF) {
155 enc->enc_pic.h264_enc_params.lsm_reference_pictures[1].list = 1;
156 enc->enc_pic.h264_enc_params.lsm_reference_pictures[1].list_index = 0;
157 enc->enc_pic.h264_enc_params.ref_list1[0] =
158 enc->enc_pic.h264_enc_params.l1_reference_picture0_index;
159 enc->enc_pic.h264_enc_params.num_active_references_l1 = 1;
160 } else {
161 enc->enc_pic.h264_enc_params.lsm_reference_pictures[1].list = 0;
162 enc->enc_pic.h264_enc_params.lsm_reference_pictures[1].list_index = 0xFFFFFFFF;
163 enc->enc_pic.h264_enc_params.ref_list0[1] = 0;
164 enc->enc_pic.h264_enc_params.ref_list1[0] = 0;
165 enc->enc_pic.h264_enc_params.num_active_references_l1 = 0;
166 }
167
168 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
169 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
170 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_pic_order_cnt);
171 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.is_reference);
172 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.is_long_term);
173 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
174 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.ref_list0[0]);
175 for (int i = 1; i < RENCODE_H264_MAX_REFERENCE_LIST_SIZE; i++)
176 RADEON_ENC_CS(0x00000000);
177 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.num_active_references_l0);
178 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.ref_list1[0]);
179 for (int i = 1; i < RENCODE_H264_MAX_REFERENCE_LIST_SIZE; i++)
180 RADEON_ENC_CS(0x00000000);
181 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.num_active_references_l1);
182 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.lsm_reference_pictures[0].list);
183 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.lsm_reference_pictures[0].list_index);
184 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.lsm_reference_pictures[1].list);
185 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.lsm_reference_pictures[1].list_index);
186 RADEON_ENC_END();
187 }
188
radeon_enc_spec_misc_av1(struct radeon_encoder * enc)189 static void radeon_enc_spec_misc_av1(struct radeon_encoder *enc)
190 {
191 /* if enabled using the input parameters, it is required to have cdef_bits
192 * > 0 */
193 if (enc->enc_pic.av1_spec_misc.cdef_mode && !!(enc->enc_pic.av1_spec_misc.cdef_bits))
194 enc->enc_pic.av1_spec_misc.cdef_mode = RENCODE_AV1_CDEF_MODE_EXPLICIT;
195 else if (enc->enc_pic.av1_spec_misc.cdef_mode)
196 enc->enc_pic.av1_spec_misc.cdef_mode = RENCODE_AV1_CDEF_MODE_DEFAULT;
197
198 RADEON_ENC_BEGIN(enc->cmd.spec_misc_av1);
199 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.palette_mode_enable);
200 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.mv_precision);
201 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_mode);
202 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_bits);
203 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_damping_minus3);
204 for (int i = 0; i < RENCODE_AV1_CDEF_MAX_NUM; i++)
205 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_y_pri_strength[i]);
206 for (int i = 0; i < RENCODE_AV1_CDEF_MAX_NUM; i++)
207 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_y_sec_strength[i]);
208 for (int i = 0; i < RENCODE_AV1_CDEF_MAX_NUM; i++)
209 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_uv_pri_strength[i]);
210 for (int i = 0; i < RENCODE_AV1_CDEF_MAX_NUM; i++)
211 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_uv_sec_strength[i]);
212 RADEON_ENC_CS(0);
213 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_cdf_update);
214 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf);
215 RADEON_ENC_CS(0);
216 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.delta_q_y_dc);
217 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.delta_q_u_dc);
218 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.delta_q_u_ac);
219 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.delta_q_v_dc);
220 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.delta_q_v_ac);
221 RADEON_ENC_CS(0);
222 RADEON_ENC_CS(0);
223 RADEON_ENC_END();
224 }
225
radeon_enc_ref_swizzle_mode(struct radeon_encoder * enc)226 static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc)
227 {
228 /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */
229 return RENCODE_REC_SWIZZLE_MODE_256B_D_VCN5;
230 }
231
radeon_enc_ctx(struct radeon_encoder * enc)232 static void radeon_enc_ctx(struct radeon_encoder *enc)
233 {
234 int i;
235 uint32_t swizzle_mode = radeon_enc_ref_swizzle_mode(enc);
236 bool is_h264 = u_reduce_video_profile(enc->base.profile)
237 == PIPE_VIDEO_FORMAT_MPEG4_AVC;
238 bool is_av1 = u_reduce_video_profile(enc->base.profile)
239 == PIPE_VIDEO_FORMAT_AV1;
240
241 RADEON_ENC_BEGIN(enc->cmd.ctx);
242 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
243 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
244
245 for (i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
246 rvcn_enc_reconstructed_picture_t *pic =
247 &enc->enc_pic.ctx_buf.reconstructed_pictures[i];
248 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
249 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
250 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
251 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
252 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
253 RADEON_ENC_CS(0);
254 RADEON_ENC_CS(swizzle_mode);
255 RADEON_ENC_READWRITE(enc->meta->res->buf, enc->meta->res->domains,
256 pic->frame_context_buffer_offset);
257 if (is_h264) {
258 RADEON_ENC_CS(pic->h264.colloc_buffer_offset);
259 RADEON_ENC_CS(0);
260 } else if (is_av1) {
261 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
262 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
263 } else {
264 RADEON_ENC_CS(0);
265 RADEON_ENC_CS(0);
266 }
267 RADEON_ENC_CS(pic->encode_metadata_offset);
268 }
269
270 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
271 rvcn_enc_reconstructed_picture_t *pic =
272 &enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i];
273 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
274 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
275 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
276 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
277 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
278 RADEON_ENC_CS(0);
279 RADEON_ENC_CS(swizzle_mode);
280 RADEON_ENC_READWRITE(enc->meta->res->buf, enc->meta->res->domains,
281 pic->frame_context_buffer_offset);
282 if (is_h264) {
283 RADEON_ENC_CS(pic->h264.colloc_buffer_offset);
284 RADEON_ENC_CS(0);
285 } else if (is_av1) {
286 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
287 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
288 } else {
289 RADEON_ENC_CS(0);
290 RADEON_ENC_CS(0);
291 }
292 RADEON_ENC_CS(pic->encode_metadata_offset);
293 }
294
295 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
296 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
297 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.red_offset);
298 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.green_offset);
299 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.blue_offset);
300 RADEON_ENC_CS(enc->enc_pic.ctx_buf.av1.av1_sdb_intermediate_context_offset);
301 RADEON_ENC_END();
302 }
303
radeon_enc_ctx_override(struct radeon_encoder * enc)304 static void radeon_enc_ctx_override(struct radeon_encoder *enc)
305 {
306 RADEON_ENC_BEGIN(enc->cmd.ctx_override);
307 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
308 rvcn_enc_reconstructed_picture_t *pic =
309 &enc->enc_pic.ctx_buf.reconstructed_pictures[i];
310 RADEON_ENC_CS(pic->luma_offset);
311 RADEON_ENC_CS(pic->chroma_offset);
312 RADEON_ENC_CS(pic->chroma_v_offset);
313 }
314 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
315 rvcn_enc_reconstructed_picture_t *pic =
316 &enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i];
317 RADEON_ENC_CS(pic->luma_offset);
318 RADEON_ENC_CS(pic->chroma_offset);
319 RADEON_ENC_CS(pic->chroma_v_offset);
320 }
321 RADEON_ENC_END();
322 }
323
radeon_enc_metadata(struct radeon_encoder * enc)324 static void radeon_enc_metadata(struct radeon_encoder *enc)
325 {
326 enc->enc_pic.metadata.two_pass_search_center_map_offset =
327 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset;
328 RADEON_ENC_BEGIN(enc->cmd.metadata);
329 RADEON_ENC_READWRITE(enc->meta->res->buf, enc->meta->res->domains, 0);
330 RADEON_ENC_CS(enc->enc_pic.metadata.two_pass_search_center_map_offset);
331 RADEON_ENC_END();
332 }
333
radeon_enc_output_format(struct radeon_encoder * enc)334 static void radeon_enc_output_format(struct radeon_encoder *enc)
335 {
336 enc->enc_pic.enc_output_format.output_chroma_subsampling = 0;
337
338 RADEON_ENC_BEGIN(enc->cmd.output_format);
339 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_volume);
340 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_range);
341 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_chroma_subsampling);
342 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_chroma_location);
343 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_bit_depth);
344 RADEON_ENC_END();
345 }
346
radeon_enc_rc_per_pic(struct radeon_encoder * enc)347 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
348 {
349 RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
350 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp_i);
351 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp_p);
352 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp_b);
353 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_i);
354 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_i);
355 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_p);
356 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_p);
357 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_b);
358 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_b);
359 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size_i);
360 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size_p);
361 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size_b);
362 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
363 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
364 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
365 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qvbr_quality_level);
366 RADEON_ENC_END();
367 }
368
radeon_enc_encode_params_hevc(struct radeon_encoder * enc)369 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
370 {
371 enc->enc_pic.hevc_enc_params.lsm_reference_pictures_list_index = 0;
372 enc->enc_pic.hevc_enc_params.ref_list0[0] =
373 enc->enc_pic.enc_params.reference_picture_index;
374 enc->enc_pic.hevc_enc_params.num_active_references_l0 =
375 (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I) ? 0 : 1;
376
377 RADEON_ENC_BEGIN(enc->cmd.enc_params_hevc);
378 RADEON_ENC_CS(enc->enc_pic.hevc_enc_params.ref_list0[0]);
379 for (int i = 1; i < RENCODE_HEVC_MAX_REFERENCE_LIST_SIZE; i++)
380 RADEON_ENC_CS(0x00000000);
381 RADEON_ENC_CS(enc->enc_pic.hevc_enc_params.num_active_references_l0);
382 RADEON_ENC_CS(enc->enc_pic.hevc_enc_params.lsm_reference_pictures_list_index);
383 RADEON_ENC_END();
384 }
385
radeon_enc_encode_params_av1(struct radeon_encoder * enc)386 static void radeon_enc_encode_params_av1(struct radeon_encoder *enc)
387 {
388 enc->enc_pic.av1_enc_params.ref_frames[0] =
389 (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I) ?
390 0xFFFFFFFF : enc->enc_pic.enc_params.reference_picture_index;
391 enc->enc_pic.av1_enc_params.lsm_reference_frame_index[0] =
392 (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I) ?
393 0xFFFFFFFF : 0;
394
395 RADEON_ENC_BEGIN(enc->cmd.enc_params_av1);
396 RADEON_ENC_CS(enc->enc_pic.av1_enc_params.ref_frames[0]);
397 for (int i = 1; i < RENCDOE_AV1_REFS_PER_FRAME; i++)
398 RADEON_ENC_CS(0xFFFFFFFF);
399 RADEON_ENC_CS(enc->enc_pic.av1_enc_params.lsm_reference_frame_index[0]);
400 RADEON_ENC_CS(0xFFFFFFFF);
401 RADEON_ENC_END();
402 }
403
radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)404 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
405 {
406 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
407 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
408 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
409 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
410 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
411 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
412 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
413 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
414 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.transform_skip_disabled);
415 RADEON_ENC_CS(0);
416 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag);
417 RADEON_ENC_END();
418 }
419
420 /* nb_sb: number of super blocks in width/height
421 * nb_tiles: number of tiles trying to partition
422 * min_nb_sb: the minimum amount of sbs in a tile
423 */
radeon_enc_is_av1_uniform_tile(uint32_t nb_sb,uint32_t nb_tiles,uint32_t min_nb_sb,struct tile_1d_layout * p)424 bool radeon_enc_is_av1_uniform_tile (uint32_t nb_sb, uint32_t nb_tiles,
425 uint32_t min_nb_sb, struct tile_1d_layout *p)
426 {
427 if (!min_nb_sb)
428 min_nb_sb = 1;
429
430 if (IS_POT_NONZERO(nb_tiles)) {
431 uint32_t nb_main_sb = DIV_ROUND_UP(nb_sb, nb_tiles);
432 uint32_t nb_main_tile = nb_sb / nb_main_sb;
433 uint32_t nb_remainder_sb = nb_sb % nb_main_sb;
434
435 /* all nb in tile has to be larger than min_nb_sb */
436 if (nb_main_sb < min_nb_sb)
437 return false;
438
439 /* if remainder exists it needs to larger than min_nb_sb */
440 if ((nb_remainder_sb && (nb_remainder_sb < min_nb_sb))
441 || ((nb_main_sb * nb_main_tile + nb_remainder_sb) != nb_sb)
442 || (nb_main_tile + !!(nb_remainder_sb) != nb_tiles))
443 return false;
444
445 p->nb_main_sb = nb_main_sb;
446 p->nb_main_tile = nb_main_tile;
447 p->nb_border_sb = nb_remainder_sb;
448 p->nb_border_tile = !!(nb_remainder_sb);
449
450 return true;
451 }
452
453 /* the number of tiles is not power of 2 */
454 return false;
455 }
456
radeon_enc_av1_tile_layout(uint32_t nb_sb,uint32_t nb_tiles,uint32_t min_nb_sb,struct tile_1d_layout * p)457 void radeon_enc_av1_tile_layout (uint32_t nb_sb, uint32_t nb_tiles, uint32_t min_nb_sb,
458 struct tile_1d_layout *p)
459 {
460 if (!min_nb_sb)
461 min_nb_sb = 1;
462
463 if (radeon_enc_is_av1_uniform_tile(nb_sb, nb_tiles, min_nb_sb, p))
464 p->uniform_tile_flag = true;
465 else {
466 uint32_t nb_main_sb = nb_sb / nb_tiles;
467
468 /* if some tile size is less than min_nb_sb need to re-divide tiles */
469 if (nb_main_sb < min_nb_sb) {
470 /* using maximum tile size (64), to recalc nb_tiles */
471 nb_tiles = DIV_ROUND_UP(nb_sb, (RENCODE_AV1_MAX_TILE_WIDTH >> 6));
472 nb_main_sb = nb_sb / nb_tiles;
473 if (radeon_enc_is_av1_uniform_tile(nb_sb, nb_tiles, min_nb_sb, p)) {
474 p->uniform_tile_flag = true;
475 return;
476 }
477 }
478
479 p->uniform_tile_flag = false;
480 if (nb_tiles <= 1) {
481 p->nb_main_sb = nb_sb;
482 p->nb_main_tile = 1;
483 p->nb_border_sb = 0;
484 p->nb_border_tile = 0;
485 } else {
486 uint32_t nb_remainder_sb = nb_sb % nb_tiles;
487
488 if (nb_remainder_sb) {
489 p->nb_main_sb = nb_main_sb + 1;
490 p->nb_main_tile = nb_remainder_sb; /* in unit of tile */
491 p->nb_border_sb = nb_main_sb;
492 p->nb_border_tile = nb_tiles - nb_remainder_sb;
493 } else {
494 p->nb_main_sb = nb_main_sb;
495 p->nb_main_tile = nb_tiles;
496 p->nb_border_sb = 0;
497 p->nb_border_tile = 0;
498 }
499 }
500 }
501 }
502
503 /* num_tile_cols and num_tile_rows will be changed if not fit */
radeon_enc_av1_tile_default(struct radeon_encoder * enc,uint32_t * num_tile_cols,uint32_t * num_tile_rows)504 static void radeon_enc_av1_tile_default(struct radeon_encoder *enc,
505 uint32_t *num_tile_cols,
506 uint32_t *num_tile_rows)
507 {
508 struct tile_1d_layout tile_layout;
509 uint32_t i;
510 bool uniform_col, uniform_row;
511 rvcn_enc_av1_tile_config_t *p_config = &enc->enc_pic.av1_tile_config;
512 uint32_t frame_width_in_sb =
513 DIV_ROUND_UP(enc->enc_pic.pic_width_in_luma_samples, PIPE_AV1_ENC_SB_SIZE);
514 uint32_t frame_height_in_sb =
515 DIV_ROUND_UP(enc->enc_pic.pic_height_in_luma_samples, PIPE_AV1_ENC_SB_SIZE);
516 uint32_t min_tile_width_in_sb = RENCODE_AV1_MIN_TILE_WIDTH >> 6;
517 uint32_t max_tile_area_sb = RENCODE_AV1_MAX_TILE_AREA >> (2 * 6);
518 uint32_t max_tile_width_in_sb = RENCODE_AV1_MAX_TILE_WIDTH >> 6;
519 uint32_t widest_tiles_in_sb = 0;
520 uint32_t max_tile_ares_in_sb = 0;
521 uint32_t max_tile_height_in_sb = 0;
522 uint32_t min_log2_tiles_width_in_sb =
523 radeon_enc_av1_tile_log2(max_tile_width_in_sb, frame_width_in_sb);
524 uint32_t min_log2_tiles = MAX2(min_log2_tiles_width_in_sb,
525 radeon_enc_av1_tile_log2(max_tile_area_sb,
526 frame_width_in_sb * frame_height_in_sb));
527
528 radeon_enc_av1_tile_layout(frame_width_in_sb, *num_tile_cols,
529 min_tile_width_in_sb, &tile_layout);
530
531 *num_tile_cols = tile_layout.nb_main_tile + tile_layout.nb_border_tile;
532 uniform_col = tile_layout.uniform_tile_flag;
533
534 for (i = 0; i < tile_layout.nb_main_tile; i++) {
535 p_config->tile_widths[i] = tile_layout.nb_main_sb;
536 widest_tiles_in_sb = MAX2(p_config->tile_widths[i], widest_tiles_in_sb);
537 }
538
539 for (i = 0; i < tile_layout.nb_border_tile; i++) {
540 p_config->tile_widths[i + tile_layout.nb_main_tile] = tile_layout.nb_border_sb;
541 widest_tiles_in_sb = MAX2(p_config->tile_widths[i], widest_tiles_in_sb);
542 }
543
544 if (min_log2_tiles)
545 max_tile_ares_in_sb = (frame_width_in_sb * frame_height_in_sb)
546 >> (min_log2_tiles + 1);
547 else
548 max_tile_ares_in_sb = frame_width_in_sb * frame_height_in_sb;
549
550 max_tile_height_in_sb = DIV_ROUND_UP(max_tile_ares_in_sb, widest_tiles_in_sb);
551 *num_tile_rows = MAX2(*num_tile_rows,
552 DIV_ROUND_UP(frame_height_in_sb, max_tile_height_in_sb));
553
554 radeon_enc_av1_tile_layout(frame_height_in_sb, *num_tile_rows, 1, &tile_layout);
555 *num_tile_rows = tile_layout.nb_main_tile + tile_layout.nb_border_tile;
556 uniform_row = tile_layout.uniform_tile_flag;
557
558 for (i = 0; i < tile_layout.nb_main_tile; i++)
559 p_config->tile_height[i] = tile_layout.nb_main_sb;
560
561 for (i = 0; i < tile_layout.nb_border_tile; i++)
562 p_config->tile_height[i + tile_layout.nb_main_tile] = tile_layout.nb_border_sb;
563
564 p_config->uniform_tile_spacing = !!(uniform_col && uniform_row);
565
566 if (enc->enc_pic.is_obu_frame) {
567 p_config->num_tile_groups = 1;
568 p_config->tile_groups[0].start = 0;
569 p_config->tile_groups[0].end = (*num_tile_rows) * (*num_tile_cols) - 1;
570 } else {
571 p_config->num_tile_groups = (*num_tile_rows) * (*num_tile_cols);
572 for (int32_t i = 0; i < *num_tile_rows; i++)
573 for (int32_t j = 0; j < *num_tile_cols; j++) {
574 int32_t k = *num_tile_cols * i + j;
575 p_config->tile_groups[k].start = k;
576 p_config->tile_groups[k].end = k;
577 }
578 }
579 }
580
radeon_enc_tile_config_av1(struct radeon_encoder * enc)581 static void radeon_enc_tile_config_av1(struct radeon_encoder *enc)
582 {
583 /* It needs to check if the input tile setting meet the current capability
584 * or not, if not then regenerate the setting, if needed at the corresponding
585 * variables for obu instruction to program headers easier and consistent
586 * with this logic */
587
588 rvcn_enc_av1_tile_config_t *p_config = &enc->enc_pic.av1_tile_config;
589 uint32_t i = 0;
590 uint32_t frame_width_in_sb =
591 DIV_ROUND_UP(enc->enc_pic.pic_width_in_luma_samples, PIPE_AV1_ENC_SB_SIZE);
592 uint32_t min_tile_width_in_sb = RENCODE_AV1_MIN_TILE_WIDTH >> 6;
593 uint32_t max_tile_num_in_width = frame_width_in_sb / min_tile_width_in_sb;
594 uint32_t max_tile_width_in_sb = RENCODE_AV1_MAX_TILE_WIDTH >> 6;
595 uint32_t min_tile_num_in_width = DIV_ROUND_UP(frame_width_in_sb, max_tile_width_in_sb);
596 uint32_t num_tile_cols, num_tile_rows;
597
598 num_tile_cols = CLAMP(p_config->num_tile_cols,
599 MAX2(1, min_tile_num_in_width),
600 MIN2(RENCODE_AV1_TILE_CONFIG_MAX_NUM_COLS, max_tile_num_in_width));
601 /* legacy way of splitting tiles, if width is less than or equal to 64 sbs, it cannot be
602 * split */
603 if (enc->enc_pic.av1_tile_splitting_legacy_flag)
604 num_tile_cols = (frame_width_in_sb <= 64) ? 1 : num_tile_cols;
605
606 num_tile_rows = CLAMP(p_config->num_tile_rows,
607 1, RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS);
608
609 p_config->apply_app_setting = false;
610
611 /* if no adjust necessary then use user's setting */
612 if (num_tile_rows == p_config->num_tile_rows &&
613 num_tile_cols == p_config->num_tile_cols) {
614 for (i = 0; i < num_tile_cols; i++) {
615 if (p_config->tile_widths[i] <= min_tile_width_in_sb)
616 break;
617 }
618 if (i == num_tile_cols)
619 p_config->apply_app_setting = true;
620 }
621 p_config->tile_size_bytes_minus_1 = 3; /* fixed value */
622
623 if (p_config->apply_app_setting && p_config->context_update_tile_id)
624 p_config->context_update_tile_id_mode = RENCODE_AV1_CONTEXT_UPDATE_TILE_ID_MODE_CUSTOMIZED;
625 else
626 p_config->context_update_tile_id_mode = RENCODE_AV1_CONTEXT_UPDATE_TILE_ID_MODE_DEFAULT;
627
628 if (!p_config->apply_app_setting) {
629 radeon_enc_av1_tile_default(enc, &num_tile_cols, &num_tile_rows);
630
631 /* re-layout tile */
632 p_config->num_tile_cols = num_tile_cols;
633 p_config->num_tile_rows = num_tile_rows;
634 }
635
636 RADEON_ENC_BEGIN(enc->cmd.tile_config_av1);
637 RADEON_ENC_CS(p_config->num_tile_cols);
638 RADEON_ENC_CS(p_config->num_tile_rows);
639 for (i = 0; i < RENCODE_AV1_TILE_CONFIG_MAX_NUM_COLS; i++)
640 RADEON_ENC_CS(p_config->tile_widths[i]);
641 for (i = 0; i < RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS; i++)
642 RADEON_ENC_CS(p_config->tile_height[i]);
643 p_config->num_tile_groups = MIN2(p_config->num_tile_groups,
644 p_config->num_tile_cols * p_config->num_tile_rows);
645 RADEON_ENC_CS(p_config->num_tile_groups);
646 for (i = 0;
647 i < RENCODE_AV1_TILE_CONFIG_MAX_NUM_COLS * RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS;
648 i++ ) {
649 RADEON_ENC_CS(p_config->tile_groups[i].start);
650 RADEON_ENC_CS(p_config->tile_groups[i].end);
651 }
652 RADEON_ENC_CS(p_config->context_update_tile_id_mode);
653 RADEON_ENC_CS(p_config->context_update_tile_id);
654 RADEON_ENC_CS(p_config->tile_size_bytes_minus_1);
655 RADEON_ENC_END();
656 }
657
radeon_enc_av1_tile_info(struct radeon_encoder * enc)658 static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
659 {
660 rvcn_enc_av1_tile_config_t *p_config = &enc->enc_pic.av1_tile_config;
661 uint32_t i = 0;
662 uint32_t sbCols = DIV_ROUND_UP(enc->enc_pic.pic_width_in_luma_samples, PIPE_AV1_ENC_SB_SIZE);
663 uint32_t sbRows = DIV_ROUND_UP(enc->enc_pic.pic_height_in_luma_samples, PIPE_AV1_ENC_SB_SIZE);
664 uint32_t maxTileWidthSb = RENCODE_AV1_MAX_TILE_WIDTH >> 6;
665 uint32_t maxTileAreaSb = RENCODE_AV1_MAX_TILE_AREA >> (2 * 6);
666 uint32_t minLog2TileCols = radeon_enc_av1_tile_log2(maxTileWidthSb, sbCols);
667 uint32_t minLog2Tiles = MAX2(minLog2TileCols,
668 radeon_enc_av1_tile_log2(maxTileAreaSb, sbRows * sbCols));
669 uint32_t TileColsLog2, TileRowsLog2;
670
671 TileColsLog2 = util_logbase2_ceil(p_config->num_tile_cols);
672 TileRowsLog2 = util_logbase2_ceil(p_config->num_tile_rows);
673
674 radeon_enc_code_fixed_bits(enc, p_config->uniform_tile_spacing, 1);
675 if (p_config->uniform_tile_spacing) {
676 for ( i = minLog2TileCols; i < TileColsLog2; i++)
677 radeon_enc_code_fixed_bits(enc, 1, 1);
678
679 radeon_enc_code_fixed_bits(enc, 0, 1);
680
681 for ( i = minLog2Tiles - TileColsLog2; i < TileRowsLog2; i++)
682 radeon_enc_code_fixed_bits(enc, 1, 1);
683
684 radeon_enc_code_fixed_bits(enc, 0, 1);
685 } else {
686 uint32_t widestTileSb = 0;
687 uint32_t maxWidthInSb = 0;
688 uint32_t maxHeightInSb = 0;
689 uint32_t maxTileHeightSb = 0;
690 uint32_t startSb = 0;
691
692 for (i = 0; i < p_config->num_tile_cols; i++) {
693 maxWidthInSb = MIN2(sbCols - startSb, maxTileWidthSb);
694 radeon_enc_code_ns(enc, p_config->tile_widths[i] - 1, maxWidthInSb);
695 startSb += p_config->tile_widths[i];
696 widestTileSb = MAX2( p_config->tile_widths[i], widestTileSb);
697 }
698
699 if (minLog2Tiles > 0)
700 maxTileAreaSb = (sbRows * sbCols) >> (minLog2Tiles + 1);
701 else
702 maxTileAreaSb = sbRows * sbCols;
703
704 maxTileHeightSb = MAX2( maxTileAreaSb / widestTileSb, 1);
705 startSb = 0;
706
707 for (i = 0; i < p_config->num_tile_rows; i++) {
708 maxHeightInSb = MIN2(sbRows - startSb, maxTileHeightSb);
709 radeon_enc_code_ns(enc, p_config->tile_height[i] - 1, maxHeightInSb);
710 startSb += p_config->tile_height[i];
711 }
712 }
713
714 if (TileColsLog2 > 0 || TileRowsLog2 > 0) {
715 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID, 0);
716
717 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
718
719 radeon_enc_code_fixed_bits(enc, p_config->tile_size_bytes_minus_1, 2);
720 }
721 }
722
radeon_enc_av1_write_delta_q(struct radeon_encoder * enc,int32_t q)723 static void radeon_enc_av1_write_delta_q(struct radeon_encoder *enc, int32_t q)
724 {
725 radeon_enc_code_fixed_bits(enc, !!(q), 1);
726
727 if (q)
728 radeon_enc_code_fixed_bits(enc, q, ( 1 + 6 ));
729 }
730
radeon_enc_av1_quantization_params(struct radeon_encoder * enc)731 static void radeon_enc_av1_quantization_params(struct radeon_encoder *enc)
732 {
733 rvcn_enc_av1_spec_misc_t *p = &enc->enc_pic.av1_spec_misc;
734
735 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX, 0);
736
737 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
738
739 radeon_enc_av1_write_delta_q(enc, p->delta_q_y_dc);
740
741 /* only support multi-planes at the time */
742 if (p->separate_delta_q)
743 radeon_enc_code_fixed_bits(enc, 1, 1);
744
745 radeon_enc_av1_write_delta_q(enc, p->delta_q_u_dc);
746 radeon_enc_av1_write_delta_q(enc, p->delta_q_u_ac);
747
748 if (p->separate_delta_q) {
749 radeon_enc_av1_write_delta_q(enc, p->delta_q_v_dc);
750 radeon_enc_av1_write_delta_q(enc, p->delta_q_v_ac);
751 }
752
753 /* using qmatrix */
754 radeon_enc_code_fixed_bits(enc, 0, 1);
755 }
756
radeon_enc_av1_frame_header(struct radeon_encoder * enc,bool frame_header)757 static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_header)
758 {
759 uint32_t i;
760 bool show_existing = false;
761 bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
762 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
763 uint32_t obu_type = frame_header ? RENCODE_OBU_TYPE_FRAME_HEADER
764 : RENCODE_OBU_TYPE_FRAME;
765
766 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
767
768 radeon_enc_av1_obu_header(enc, obu_type);
769
770 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
771
772 /* uncompressed_header() */
773 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
774 /* show_existing_frame */
775 show_existing = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING;
776 radeon_enc_code_fixed_bits(enc, show_existing ? 1 : 0, 1);
777 /* if (show_existing_frame == 1) */
778 if(show_existing) {
779 /* frame_to_show_map_idx */
780 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_to_show_map_index, 3);
781 /* display_frame_id */
782 if (enc->enc_pic.frame_id_numbers_present)
783 radeon_enc_code_fixed_bits(enc, enc->enc_pic.display_frame_id,
784 RENCODE_AV1_DELTA_FRAME_ID_LENGTH +
785 RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH);
786 } else {
787 /* frame_type */
788 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_type, 2);
789 /* show_frame */
790 radeon_enc_code_fixed_bits(enc, 1, 1);
791 bool error_resilient_mode = false;
792 if ((enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH) ||
793 (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY))
794 error_resilient_mode = true;
795 else {
796 /* error_resilient_mode */
797 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
798 error_resilient_mode = enc->enc_pic.enable_error_resilient_mode;
799 }
800 /* disable_cdf_update */
801 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
802
803 bool allow_screen_content_tools = false;
804 if (!enc->enc_pic.disable_screen_content_tools) {
805 /* allow_screen_content_tools */
806 allow_screen_content_tools = enc->enc_pic.av1_spec_misc.palette_mode_enable ||
807 enc->enc_pic.force_integer_mv;
808 radeon_enc_code_fixed_bits(enc, allow_screen_content_tools ? 1 : 0, 1);
809 }
810
811 if (allow_screen_content_tools)
812 /* force_integer_mv */
813 radeon_enc_code_fixed_bits(enc, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
814
815 if (enc->enc_pic.frame_id_numbers_present)
816 /* current_frame_id */
817 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_id,
818 RENCODE_AV1_DELTA_FRAME_ID_LENGTH +
819 RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH);
820
821 bool frame_size_override = false;
822 if (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH)
823 frame_size_override = true;
824 else {
825 /* frame_size_override_flag */
826 frame_size_override = false;
827 radeon_enc_code_fixed_bits(enc, 0, 1);
828 }
829
830 if (enc->enc_pic.enable_order_hint)
831 radeon_enc_code_fixed_bits(enc, enc->enc_pic.order_hint, enc->enc_pic.order_hint_bits);
832
833 if (!frame_is_intra && !error_resilient_mode)
834 /* primary_ref_frame */
835 radeon_enc_code_fixed_bits(enc, 0, 3); /* always LAST_FRAME(1) */
836
837 if ((enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SWITCH) &&
838 (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_KEY))
839 /* refresh_frame_flags */
840 radeon_enc_code_fixed_bits(enc, enc->enc_pic.refresh_frame_flags, 8);
841
842 if ((!frame_is_intra || enc->enc_pic.refresh_frame_flags != 0xff) &&
843 error_resilient_mode && enc->enc_pic.enable_order_hint)
844 for (i = 0; i < RENCDOE_AV1_NUM_REF_FRAMES; i++)
845 /* ref_order_hint */
846 radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_order_hint[i], enc->enc_pic.order_hint_bits);
847
848 if (frame_is_intra) {
849 /* render_and_frame_size_different */
850 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_render_size ? 1 : 0, 1);
851 if (enc->enc_pic.enable_render_size) {
852 /* render_width_minus_1 */
853 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_width - 1, 16);
854 /* render_height_minus_1 */
855 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_height - 1, 16);
856 }
857 if (!enc->enc_pic.disable_screen_content_tools &&
858 (enc->enc_pic.av1_spec_misc.palette_mode_enable || enc->enc_pic.force_integer_mv))
859 /* allow_intrabc */
860 radeon_enc_code_fixed_bits(enc, 0, 1);
861 } else {
862 if (enc->enc_pic.enable_order_hint)
863 /* frame_refs_short_signaling */
864 radeon_enc_code_fixed_bits(enc, 0, 1);
865 for (i = 0; i < RENCDOE_AV1_REFS_PER_FRAME; i++) {
866 /* ref_frame_idx */
867 radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_frame_index, 3);
868 if (enc->enc_pic.frame_id_numbers_present)
869 radeon_enc_code_fixed_bits(enc,
870 enc->enc_pic.reference_delta_frame_id - 1,
871 RENCODE_AV1_DELTA_FRAME_ID_LENGTH);
872 }
873
874 if (frame_size_override && !error_resilient_mode)
875 /* found_ref */
876 radeon_enc_code_fixed_bits(enc, 1, 1);
877 else {
878 if(frame_size_override) {
879 /* frame_width_minus_1 */
880 uint32_t used_bits =
881 radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_width - 1);
882 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_width - 1,
883 used_bits);
884 /* frame_height_minus_1 */
885 used_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_height - 1);
886 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_height - 1,
887 used_bits);
888 }
889 /* render_and_frame_size_different */
890 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_render_size ? 1 : 0, 1);
891 if (enc->enc_pic.enable_render_size) {
892 /* render_width_minus_1 */
893 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_width - 1, 16);
894 /* render_height_minus_1 */
895 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_height - 1, 16);
896 }
897 }
898
899 if (enc->enc_pic.disable_screen_content_tools || !enc->enc_pic.force_integer_mv)
900 /* allow_high_precision_mv */
901 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
902
903 /* read_interpolation_filter */
904 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
905
906 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
907 /* is_motion_mode_switchable */
908 radeon_enc_code_fixed_bits(enc, 0, 1);
909 }
910
911 if (!enc->enc_pic.av1_spec_misc.disable_cdf_update)
912 /* disable_frame_end_update_cdf */
913 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
914
915 /* tile_info */
916 radeon_enc_av1_tile_info(enc);
917 /* quantization_params */
918 radeon_enc_av1_quantization_params(enc);
919 /* segmentation_enable */
920 radeon_enc_code_fixed_bits(enc, 0, 1);
921 /* delta_q_params */
922 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
923 /* delta_lf_params */
924 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
925 /* loop_filter_params */
926 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
927 /* cdef_params */
928 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
929 /* lr_params */
930 /* read_tx_mode */
931 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
932
933 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
934 if (!frame_is_intra)
935 /* reference_select */
936 radeon_enc_code_fixed_bits(enc, 0, 1);
937
938 radeon_enc_code_fixed_bits(enc, 0, 1);
939 if (!frame_is_intra)
940 for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
941 /* is_global */
942 radeon_enc_code_fixed_bits(enc, 0, 1);
943 /* film_grain_params() */
944 }
945 }
946
radeon_enc_obu_instruction(struct radeon_encoder * enc)947 static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
948 {
949 bool frame_header = !enc->enc_pic.is_obu_frame ||
950 (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING);
951
952 radeon_enc_reset(enc);
953 RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
954 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
955
956 radeon_enc_av1_temporal_delimiter(enc);
957 if (enc->enc_pic.need_av1_seq || enc->enc_pic.need_sequence_header)
958 radeon_enc_av1_sequence_header(enc, enc->enc_pic.av1_spec_misc.separate_delta_q);
959
960 /* if others OBU types are needed such as meta data, then they need to be byte aligned and added here
961 *
962 * if (others)
963 * radeon_enc_av1_others(enc); */
964 radeon_enc_av1_metadata_obu(enc);
965
966 radeon_enc_av1_bs_instruction_type(enc,
967 RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
968 frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
969 : RENCODE_OBU_START_TYPE_FRAME);
970
971 radeon_enc_av1_frame_header(enc, frame_header);
972
973 if (!frame_header && (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING))
974 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
975
976 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
977
978 if (frame_header && (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING))
979 radeon_enc_av1_tile_group(enc);
980
981 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
982 RADEON_ENC_END();
983 }
984
radeon_enc_session_init(struct radeon_encoder * enc)985 static void radeon_enc_session_init(struct radeon_encoder *enc)
986 {
987 switch (u_reduce_video_profile(enc->base.profile)) {
988 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
989 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
990 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
991 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
992
993 enc->enc_pic.session_init.padding_width =
994 (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2;
995 enc->enc_pic.session_init.padding_height =
996 (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2;
997 break;
998 case PIPE_VIDEO_FORMAT_HEVC:
999 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
1000 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
1001 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
1002 enc->enc_pic.session_init.padding_width =
1003 (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2;
1004 enc->enc_pic.session_init.padding_height =
1005 (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2;
1006 break;
1007 case PIPE_VIDEO_FORMAT_AV1:
1008 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_AV1;
1009 enc->enc_pic.session_init.aligned_picture_width =
1010 align(enc->enc_pic.pic_width_in_luma_samples, 8);
1011 enc->enc_pic.session_init.aligned_picture_height =
1012 align(enc->enc_pic.pic_height_in_luma_samples, 2);
1013
1014 enc->enc_pic.session_init.padding_width =
1015 enc->enc_pic.session_init.aligned_picture_width -
1016 enc->enc_pic.pic_width_in_luma_samples;
1017 enc->enc_pic.session_init.padding_height =
1018 enc->enc_pic.session_init.aligned_picture_height -
1019 enc->enc_pic.pic_height_in_luma_samples;
1020
1021 if (enc->enc_pic.enable_render_size)
1022 enc->enc_pic.enable_render_size =
1023 (enc->enc_pic.session_init.aligned_picture_width !=
1024 enc->enc_pic.render_width) ||
1025 (enc->enc_pic.session_init.aligned_picture_height !=
1026 enc->enc_pic.render_height);
1027 break;
1028 default:
1029 assert(0);
1030 break;
1031 }
1032
1033 enc->enc_pic.session_init.slice_output_enabled = 0;
1034 enc->enc_pic.session_init.display_remote = 0;
1035 enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode;
1036 enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode);
1037
1038 RADEON_ENC_BEGIN(enc->cmd.session_init);
1039 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
1040 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
1041 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
1042 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
1043 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
1044 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
1045 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
1046 RADEON_ENC_CS(enc->enc_pic.session_init.slice_output_enabled);
1047 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
1048 RADEON_ENC_END();
1049 }
1050
radeon_enc_5_0_init(struct radeon_encoder * enc)1051 void radeon_enc_5_0_init(struct radeon_encoder *enc)
1052 {
1053 radeon_enc_4_0_init(enc);
1054
1055 enc->session_init = radeon_enc_session_init;
1056 enc->ctx = radeon_enc_ctx;
1057 enc->output_format = radeon_enc_output_format;
1058 enc->metadata = radeon_enc_metadata;
1059 enc->ctx_override = radeon_enc_ctx_override;
1060 enc->encode_params = radeon_enc_encode_params;
1061 enc->rc_per_pic = radeon_enc_rc_per_pic;
1062
1063 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1064 enc->spec_misc = radeon_enc_spec_misc;
1065 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1066 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1067 enc->encode_params_codec_spec = radeon_enc_encode_params_hevc;
1068 enc->spec_misc = radeon_enc_spec_misc_hevc;
1069 enc->cmd.enc_params_hevc = RENCODE_IB_PARAM_HEVC_ENCODE_PARAMS;
1070 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_AV1) {
1071 enc->cdf_default_table = radeon_enc_cdf_default_table;
1072 enc->spec_misc = radeon_enc_spec_misc_av1;
1073 enc->tile_config = radeon_enc_tile_config_av1;
1074 enc->obu_instructions = radeon_enc_obu_instruction;
1075 enc->encode_params_codec_spec = radeon_enc_encode_params_av1;
1076 enc->cmd.tile_config_av1 = RENCODE_AV1_IB_PARAM_TILE_CONFIG;
1077 enc->cmd.bitstream_instruction_av1 = RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION;
1078 enc->cmd.enc_params_av1 = RENCODE_IB_PARAM_AV1_ENCODE_PARAMS;
1079 }
1080
1081 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1082 enc->cmd.metadata = RENCODE_IB_PARAM_METADATA_BUFFER;
1083 enc->cmd.ctx_override = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER_OVERRIDE;
1084
1085 enc->enc_pic.session_info.interface_version =
1086 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1087 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1088 }
1089