1 /*
2 * Copyright © 2011 Marek Olšák <[email protected]>
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #ifndef RADEON_DRM_CS_H
8 #define RADEON_DRM_CS_H
9
10 #include "radeon_drm_bo.h"
11
12 struct radeon_ctx {
13 struct radeon_drm_winsys *ws;
14 uint32_t gpu_reset_counter;
15 };
16
17 struct radeon_bo_item {
18 struct radeon_bo *bo;
19 union {
20 struct {
21 uint32_t priority_usage;
22 } real;
23 struct {
24 unsigned real_idx;
25 } slab;
26 } u;
27 };
28
29 struct radeon_cs_context {
30 uint32_t buf[16 * 1024];
31
32 int fd;
33 struct drm_radeon_cs cs;
34 struct drm_radeon_cs_chunk chunks[3];
35 uint64_t chunk_array[3];
36 uint32_t flags[2];
37
38 /* Buffers. */
39 unsigned max_relocs;
40 unsigned num_relocs;
41 unsigned num_validated_relocs;
42 struct radeon_bo_item *relocs_bo;
43 struct drm_radeon_cs_reloc *relocs;
44
45 unsigned num_slab_buffers;
46 unsigned max_slab_buffers;
47 struct radeon_bo_item *slab_buffers;
48
49 int reloc_indices_hashlist[4096];
50 };
51
52 struct radeon_drm_cs {
53 enum amd_ip_type ip_type;
54
55 /* We flip between these two CS. While one is being consumed
56 * by the kernel in another thread, the other one is being filled
57 * by the pipe driver. */
58 struct radeon_cs_context csc1;
59 struct radeon_cs_context csc2;
60 /* The currently-used CS. */
61 struct radeon_cs_context *csc;
62 /* The CS being currently-owned by the other thread. */
63 struct radeon_cs_context *cst;
64
65 /* The winsys. */
66 struct radeon_drm_winsys *ws;
67
68 /* Flush CS. */
69 void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
70 void *flush_data;
71
72 struct util_queue_fence flush_completed;
73 struct pipe_fence_handle *next_fence;
74 };
75
76 int radeon_lookup_buffer(struct radeon_winsys *rws, struct radeon_cs_context *csc,
77 struct radeon_bo *bo);
78
79 static inline struct radeon_drm_cs *
radeon_drm_cs(struct radeon_cmdbuf * rcs)80 radeon_drm_cs(struct radeon_cmdbuf *rcs)
81 {
82 return (struct radeon_drm_cs*)rcs->priv;
83 }
84
85 static inline bool
radeon_bo_is_referenced_by_cs(struct radeon_drm_cs * cs,struct radeon_bo * bo)86 radeon_bo_is_referenced_by_cs(struct radeon_drm_cs *cs,
87 struct radeon_bo *bo)
88 {
89 int num_refs = bo->num_cs_references;
90 return num_refs == bo->rws->num_cs ||
91 (num_refs && radeon_lookup_buffer(&cs->ws->base, cs->csc, bo) != -1);
92 }
93
94 static inline bool
radeon_bo_is_referenced_by_cs_for_write(struct radeon_drm_cs * cs,struct radeon_bo * bo)95 radeon_bo_is_referenced_by_cs_for_write(struct radeon_drm_cs *cs,
96 struct radeon_bo *bo)
97 {
98 int index;
99
100 if (!bo->num_cs_references)
101 return false;
102
103 index = radeon_lookup_buffer(&cs->ws->base, cs->csc, bo);
104 if (index == -1)
105 return false;
106
107 if (!bo->handle)
108 index = cs->csc->slab_buffers[index].u.slab.real_idx;
109
110 return cs->csc->relocs[index].write_domain != 0;
111 }
112
113 static inline bool
radeon_bo_is_referenced_by_any_cs(struct radeon_bo * bo)114 radeon_bo_is_referenced_by_any_cs(struct radeon_bo *bo)
115 {
116 return bo->num_cs_references != 0;
117 }
118
119 void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs);
120 void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws);
121 void radeon_drm_cs_emit_ioctl_oneshot(void *job, void *gdata, int thread_index);
122
123 #endif
124