1 /*********************************************************************************************************************** 2 * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 #ifndef BSP_MODULE_H 22 #define BSP_MODULE_H 23 24 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 25 FSP_HEADER 26 27 /*******************************************************************************************************************//** 28 * @addtogroup BSP_MCU 29 * @{ 30 **********************************************************************************************************************/ 31 32 #if BSP_FEATURE_TZ_HAS_TRUSTZONE 33 34 /* MSTPCRA is located in R_MSTP for Star devices. */ 35 #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) 36 #else 37 38 /* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ 39 #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) 40 #endif 41 42 /*******************************************************************************************************************//** 43 * Cancels the module stop state. 44 * 45 * @param ip fsp_ip_t enum value for the module to be stopped 46 * @param channel The channel. Use channel 0 for modules without channels. 47 **********************************************************************************************************************/ 48 #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 49 FSP_CRITICAL_SECTION_ENTER; \ 50 BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ 51 BSP_MSTP_REG_ ## ip(channel); \ 52 FSP_CRITICAL_SECTION_EXIT;} 53 54 /*******************************************************************************************************************//** 55 * Enables the module stop state. 56 * 57 * @param ip fsp_ip_t enum value for the module to be stopped 58 * @param channel The channel. Use channel 0 for modules without channels. 59 **********************************************************************************************************************/ 60 #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 61 FSP_CRITICAL_SECTION_ENTER; \ 62 BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ 63 BSP_MSTP_REG_ ## ip(channel); \ 64 FSP_CRITICAL_SECTION_EXIT;} 65 66 /** @} (end addtogroup BSP_MCU) */ 67 68 #if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE 69 #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD 70 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ 71 channel) ? (1U << 5U) : (1U << 6U)); 72 #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD 73 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); 74 #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD 75 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); 76 #else 77 #if (2U == BSP_FEATURE_ELC_VERSION) 78 #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE 79 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); 80 #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD 81 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); 82 #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE 83 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); 84 #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD 85 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); 86 #else 87 #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE 88 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); 89 #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) 90 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ 91 channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U)))); 92 #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE 93 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); 94 #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD 95 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); 96 #endif 97 #endif 98 99 #define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA 100 #define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); 101 #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA 102 #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); 103 #define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB 104 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); 105 #define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB 106 #define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); 107 #define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB 108 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); 109 #define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB 110 #define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); 111 #define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB 112 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); 113 #define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB 114 #define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); 115 #define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB 116 #define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); 117 #define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB 118 #define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); 119 #define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB 120 #define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); 121 #define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB 122 #define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); 123 #define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB 124 #define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); 125 #define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB 126 #define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); 127 #define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC 128 #define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); 129 #define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC 130 #define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); 131 #define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC 132 #define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); 133 #define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC 134 #define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); 135 #define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC 136 #define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); 137 #define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC 138 #define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); 139 #define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC 140 #define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); 141 #define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC 142 #define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); 143 #define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC 144 #define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); 145 #define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC 146 #define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); 147 #define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC 148 #define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); 149 #define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC 150 #define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); 151 #define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC 152 #define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); 153 #define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC 154 #define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); 155 #define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC 156 #define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); 157 #define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC 158 #define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U)); 159 #define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC 160 #define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); 161 #define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC 162 #define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); 163 #define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC 164 #define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); 165 #define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD 166 #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); 167 #define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD 168 #define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); 169 #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) 170 #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD 171 #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); 172 #else 173 #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD 174 #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); 175 #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD 176 #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); 177 #endif 178 #define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD 179 #define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); 180 #define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD 181 #define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); 182 #define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD 183 #define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); 184 #define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD 185 #define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); 186 187 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 188 FSP_FOOTER 189 190 #endif 191