1 /***********************************************************************************************************************
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3 *
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19 **********************************************************************************************************************/
20
21 /** @} (end addtogroup BSP_MCU) */
22
23 #ifndef BSP_IRQ_H
24 #define BSP_IRQ_H
25
26 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
27 FSP_HEADER
28
29 /***********************************************************************************************************************
30 * Macro definitions
31 **********************************************************************************************************************/
32 #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES)
33
34 /***********************************************************************************************************************
35 * Typedef definitions
36 **********************************************************************************************************************/
37
38 /***********************************************************************************************************************
39 * Exported global variables
40 **********************************************************************************************************************/
41 extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
42
43 /***********************************************************************************************************************
44 * Exported global functions (to be accessed by other files)
45 **********************************************************************************************************************/
46
47 /*******************************************************************************************************************//**
48 * @brief Sets the ISR context associated with the requested IRQ.
49 *
50 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
51 * function.
52 * @param[in] p_context ISR context for IRQ.
53 **********************************************************************************************************************/
R_FSP_IsrContextSet(IRQn_Type const irq,void * p_context)54 __STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
55 {
56 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
57 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
58 gp_renesas_isr_context[irq] = p_context;
59 }
60
61 /*******************************************************************************************************************//**
62 * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit
63 * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately.
64 *
65 * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
66 * only those for the Cortex Processor Exceptions Numbers.
67 *
68 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
69 **********************************************************************************************************************/
R_BSP_IrqStatusClear(IRQn_Type irq)70 __STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq)
71 {
72 /* Clear the IR bit in the selected IELSR register. */
73 R_ICU->IELSR_b[irq].IR = 0U;
74 }
75
76 /*******************************************************************************************************************//**
77 * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt.
78 *
79 * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
80 * only those for the Cortex Processor Exceptions Numbers.
81 *
82 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
83 **********************************************************************************************************************/
R_BSP_IrqClearPending(IRQn_Type irq)84 __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
85 {
86 /* Clear the IR bit in the selected IELSR register. */
87 R_BSP_IrqStatusClear(irq);
88
89 /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system
90 * exceptions every time an interrupt is cleared in the NVIC. */
91 uint32_t _irq = (uint32_t) irq;
92 NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
93 }
94
95 /*******************************************************************************************************************//**
96 * Sets the interrupt priority and context.
97 *
98 * @param[in] irq The IRQ to configure.
99 * @param[in] priority NVIC priority of the interrupt
100 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
101 *
102 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
103 **********************************************************************************************************************/
R_BSP_IrqCfg(IRQn_Type const irq,uint32_t priority,void * p_context)104 __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
105 {
106 /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions
107 * every time a priority is configured in the NVIC. */
108 #if (4U == __CORTEX_M)
109 NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX);
110 #elif (33 == __CORTEX_M)
111 NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX);
112 #elif (23 == __CORTEX_M)
113 NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) |
114 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq)));
115 #else
116 NVIC_SetPriority(irq, priority);
117 #endif
118
119 /* Store the context. The context is recovered in the ISR. */
120 R_FSP_IsrContextSet(irq, p_context);
121 }
122
123 /*******************************************************************************************************************//**
124 * Enable the IRQ in the NVIC (Without clearing the pending bit).
125 *
126 * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex
127 * Processor Exceptions Numbers.
128 *
129 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
130 **********************************************************************************************************************/
R_BSP_IrqEnableNoClear(IRQn_Type const irq)131 __STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
132 {
133 /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions
134 * every time an interrupt is enabled in the NVIC. */
135 uint32_t _irq = (uint32_t) irq;
136 NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
137 }
138
139 /*******************************************************************************************************************//**
140 * Clears pending interrupts in both ICU and NVIC, then enables the interrupt.
141 *
142 * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed
143 * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.
144 *
145 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
146 **********************************************************************************************************************/
R_BSP_IrqEnable(IRQn_Type const irq)147 __STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
148 {
149 /* Clear pending interrupts in the ICU and NVIC. */
150 R_BSP_IrqClearPending(irq);
151
152 /* Enable the IRQ in the NVIC. */
153 R_BSP_IrqEnableNoClear(irq);
154 }
155
156 /*******************************************************************************************************************//**
157 * Disables interrupts in the NVIC.
158 *
159 * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are
160 * only those for the Cortex Processor Exceptions Numbers.
161 *
162 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
163 **********************************************************************************************************************/
R_BSP_IrqDisable(IRQn_Type const irq)164 __STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
165 {
166 /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system
167 * exceptions every time an interrupt is cleared in the NVIC. */
168 uint32_t _irq = (uint32_t) irq;
169 NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
170
171 __DSB();
172 __ISB();
173 }
174
175 /*******************************************************************************************************************//**
176 * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
177 *
178 * @param[in] irq Interrupt number.
179 * @param[in] priority NVIC priority of the interrupt
180 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
181 *
182 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
183 **********************************************************************************************************************/
R_BSP_IrqCfgEnable(IRQn_Type const irq,uint32_t priority,void * p_context)184 __STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
185 {
186 R_BSP_IrqCfg(irq, priority, p_context);
187 R_BSP_IrqEnable(irq);
188 }
189
190 /*******************************************************************************************************************//**
191 * @brief Finds the ISR context associated with the requested IRQ.
192 *
193 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
194 * function.
195 * @return ISR context for IRQ.
196 **********************************************************************************************************************/
R_FSP_IsrContextGet(IRQn_Type const irq)197 __STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
198 {
199 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
200 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
201 return gp_renesas_isr_context[irq];
202 }
203
204 /*******************************************************************************************************************//**
205 * @internal
206 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
207 * @ingroup RENESAS_INTERNAL
208 * @{
209 **********************************************************************************************************************/
210
211 /* Public functions defined in bsp.h */
212 void bsp_irq_cfg(void); // Used internally by BSP
213
214 /** @} (end addtogroup BSP_MCU_PRV) */
215
216 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
217 FSP_FOOTER
218
219 #endif
220