1 /*********************************************************************************************************************** 2 * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 #ifndef BSP_CLOCKS_H 22 #define BSP_CLOCKS_H 23 24 /*********************************************************************************************************************** 25 * Includes 26 **********************************************************************************************************************/ 27 #include "bsp_clock_cfg.h" 28 #include "bsp_api.h" 29 30 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 31 FSP_HEADER 32 33 /*********************************************************************************************************************** 34 * Macro definitions 35 **********************************************************************************************************************/ 36 37 /* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ 38 /* Must match SCKCR.CKSEL values. */ 39 #define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. 40 #define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. 41 #define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. 42 #define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. 43 #define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. 44 #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. 45 #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. 46 47 /* PLLs are not supported in the following scenarios: 48 * - When using low voltage mode 49 * - When using an MCU that does not have a PLL 50 * - When the PLL only accepts the main oscillator as a source and XTAL is not used 51 */ 52 #if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ 53 !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) 54 #define BSP_PRV_PLL_SUPPORTED (1) 55 #if BSP_FEATURE_CGC_HAS_PLL2 56 #define BSP_PRV_PLL2_SUPPORTED (1) 57 #else 58 #define BSP_PRV_PLL2_SUPPORTED (0) 59 #endif 60 #else 61 #define BSP_PRV_PLL_SUPPORTED (0) 62 #define BSP_PRV_PLL2_SUPPORTED (0) 63 #endif 64 65 /* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency 66 * calculated here is also used to initialize the g_clock_freq array. */ 67 #if BSP_PRV_PLL_SUPPORTED 68 #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) 69 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) 70 #else 71 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) 72 #endif 73 #endif 74 #if BSP_PRV_PLL2_SUPPORTED 75 #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE 76 #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) 77 #else 78 #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) 79 #endif 80 #endif 81 82 /* Frequencies of clocks with fixed freqencies. */ 83 #define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz 84 #define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz 85 #define BSP_MOCO_FREQ_HZ (8000000U) // MOCO frequency is fixed at 8 MHz 86 87 #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE 88 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) 89 #elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE 90 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) 91 #elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE 92 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) 93 #elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE 94 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) 95 #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE 96 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) 97 #elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE 98 #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) 99 #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE 100 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) 101 #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE 102 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) 103 #endif 104 #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ 105 (BSP_CFG_PLL_DIV + 1U)) 106 #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) 107 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) 108 #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ 109 (BSP_CFG_PLL_DIV)) 110 #endif 111 #endif 112 113 /* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have 114 * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ 115 #define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_ICLK_DIV) 116 #define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV) 117 #define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV) 118 #define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKC_DIV) 119 #define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV) 120 #define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_BCLK_DIV) 121 #define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_FCLK_DIV) 122 123 /* System clock divider options. */ 124 #define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. 125 #define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. 126 #define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. 127 #define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. 128 #define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. 129 #define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. 130 #define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. 131 #define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). 132 133 /* USB clock divider options. */ 134 #define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 135 #define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 136 #define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 137 138 /* OCTA clock divider options. */ 139 #define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 140 #define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 141 #define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 142 #define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 143 #define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 144 145 /* CANFD clock divider options. */ 146 #define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 147 #define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 148 #define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 149 #define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 150 #define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 151 152 /* SCISPI clock divider options. */ 153 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 154 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 155 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 156 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 157 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 158 159 /* GPT clock divider options. */ 160 #define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 161 #define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 162 #define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 163 #define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 164 #define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 165 166 /* IIC clock divider options. */ 167 #define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 168 #define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 169 #define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 170 #define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 171 #define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 172 173 /* PLL divider options. */ 174 #define BSP_CLOCKS_PLL_DIV_1 (0) 175 #define BSP_CLOCKS_PLL_DIV_2 (1) 176 #define BSP_CLOCKS_PLL_DIV_3 (2) 177 #define BSP_CLOCKS_PLL_DIV_4 (2) 178 179 /* PLL multiplier options. */ 180 #define BSP_CLOCKS_PLL_MUL_8_0 (0xF) 181 #define BSP_CLOCKS_PLL_MUL_9_0 (0x11) 182 #define BSP_CLOCKS_PLL_MUL_10_0 (0x13) 183 #define BSP_CLOCKS_PLL_MUL_10_5 (0x14) 184 #define BSP_CLOCKS_PLL_MUL_11_0 (0x15) 185 #define BSP_CLOCKS_PLL_MUL_11_5 (0x16) 186 #define BSP_CLOCKS_PLL_MUL_12_0 (0x17) 187 #define BSP_CLOCKS_PLL_MUL_12_5 (0x18) 188 #define BSP_CLOCKS_PLL_MUL_13_0 (0x19) 189 #define BSP_CLOCKS_PLL_MUL_13_5 (0x1A) 190 #define BSP_CLOCKS_PLL_MUL_14_0 (0x1B) 191 #define BSP_CLOCKS_PLL_MUL_14_5 (0x1c) 192 #define BSP_CLOCKS_PLL_MUL_15_0 (0x1d) 193 #define BSP_CLOCKS_PLL_MUL_15_5 (0x1e) 194 #define BSP_CLOCKS_PLL_MUL_16_0 (0x1f) 195 #define BSP_CLOCKS_PLL_MUL_16_5 (0x20) 196 #define BSP_CLOCKS_PLL_MUL_17_0 (0x21) 197 #define BSP_CLOCKS_PLL_MUL_17_5 (0x22) 198 #define BSP_CLOCKS_PLL_MUL_18_0 (0x23) 199 #define BSP_CLOCKS_PLL_MUL_18_5 (0x24) 200 #define BSP_CLOCKS_PLL_MUL_19_0 (0x25) 201 #define BSP_CLOCKS_PLL_MUL_19_5 (0x26) 202 #define BSP_CLOCKS_PLL_MUL_20_0 (0x27) 203 #define BSP_CLOCKS_PLL_MUL_20_5 (0x28) 204 #define BSP_CLOCKS_PLL_MUL_21_0 (0x29) 205 #define BSP_CLOCKS_PLL_MUL_21_5 (0x2A) 206 #define BSP_CLOCKS_PLL_MUL_22_0 (0x2B) 207 #define BSP_CLOCKS_PLL_MUL_22_5 (0x2c) 208 #define BSP_CLOCKS_PLL_MUL_23_0 (0x2d) 209 #define BSP_CLOCKS_PLL_MUL_23_5 (0x2e) 210 #define BSP_CLOCKS_PLL_MUL_24_0 (0x2f) 211 #define BSP_CLOCKS_PLL_MUL_24_5 (0x30) 212 #define BSP_CLOCKS_PLL_MUL_25_0 (0x31) 213 #define BSP_CLOCKS_PLL_MUL_25_5 (0x32) 214 #define BSP_CLOCKS_PLL_MUL_26_0 (0x33) 215 #define BSP_CLOCKS_PLL_MUL_26_5 (0x34) 216 #define BSP_CLOCKS_PLL_MUL_27_0 (0x35) 217 #define BSP_CLOCKS_PLL_MUL_27_5 (0x36) 218 #define BSP_CLOCKS_PLL_MUL_28_0 (0x37) 219 #define BSP_CLOCKS_PLL_MUL_28_5 (0x38) 220 #define BSP_CLOCKS_PLL_MUL_29_0 (0x39) 221 #define BSP_CLOCKS_PLL_MUL_29_5 (0x3A) 222 #define BSP_CLOCKS_PLL_MUL_30_0 (0x3B) 223 #define BSP_CLOCKS_PLL_MUL_31_0 (0x3D) 224 225 /* Configuration option used to disable clock output. */ 226 #define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) 227 228 /* HOCO cycles per microsecond. */ 229 #define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) 230 231 /* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ 232 #if BSP_HOCO_HZ < 48000000U 233 #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) 234 #else 235 #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) 236 #endif 237 238 /* Create a mask of valid bits in SCKDIVCR. */ 239 #define BSP_PRV_SCKDIVCR_ICLK_MASK (7U << 24) 240 #if BSP_FEATURE_CGC_HAS_PCLKD 241 #define BSP_PRV_SCKDIVCR_PCLKD_MASK (7U << 0) 242 #else 243 #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) 244 #endif 245 #if BSP_FEATURE_CGC_HAS_PCLKC 246 #define BSP_PRV_SCKDIVCR_PCLKC_MASK (7U << 4) 247 #else 248 #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) 249 #endif 250 #if BSP_FEATURE_CGC_HAS_PCLKB 251 #define BSP_PRV_SCKDIVCR_PCLKB_MASK (7U << 8) 252 #else 253 #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) 254 #endif 255 #if BSP_FEATURE_CGC_HAS_PCLKA 256 #define BSP_PRV_SCKDIVCR_PCLKA_MASK (7U << 12) 257 #else 258 #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) 259 #endif 260 #if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB 261 #define BSP_PRV_SCKDIVCR_BCLK_MASK (7U << 16) 262 #else 263 #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) 264 #endif 265 #if BSP_FEATURE_CGC_HAS_FCLK 266 #define BSP_PRV_SCKDIVCR_FCLK_MASK (7U << 28) 267 #else 268 #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) 269 #endif 270 #define BSP_PRV_SCKDIVCR_MASK ((((((BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK) | \ 271 BSP_PRV_SCKDIVCR_PCLKC_MASK) | BSP_PRV_SCKDIVCR_PCLKB_MASK) | \ 272 BSP_PRV_SCKDIVCR_PCLKA_MASK) | \ 273 BSP_PRV_SCKDIVCR_BCLK_MASK) | BSP_PRV_SCKDIVCR_FCLK_MASK) 274 275 /* FLL is only used when enabled, present and the subclock is populated. */ 276 #if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED 277 #define BSP_PRV_HOCO_USE_FLL (1) 278 #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US 279 #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) 280 #endif 281 #else 282 #define BSP_PRV_HOCO_USE_FLL (0) 283 #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) 284 #endif 285 286 /* Operating power control modes. */ 287 #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed 288 #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed 289 #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage 290 #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed 291 #define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used 292 293 /*********************************************************************************************************************** 294 * Typedef definitions 295 **********************************************************************************************************************/ 296 297 #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD 298 typedef struct 299 { 300 uint32_t pll_freq; 301 } bsp_clock_update_callback_args_t; 302 303 #if defined(__ARMCC_VERSION) || defined(__ICCARM__) 304 typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * 305 p_callback_args); 306 #elif defined(__GNUC__) 307 typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * 308 p_callback_args); 309 #endif 310 311 #endif 312 313 /*********************************************************************************************************************** 314 * Exported global variables 315 **********************************************************************************************************************/ 316 317 /*********************************************************************************************************************** 318 * Exported global functions (to be accessed by other files) 319 **********************************************************************************************************************/ 320 321 /* Public functions defined in bsp.h */ 322 void bsp_clock_init(void); // Used internally by BSP 323 324 #if BSP_TZ_NONSECURE_BUILD 325 void bsp_clock_freq_var_init(void); // Used internally by BSP 326 327 #endif 328 329 #if BSP_TZ_SECURE_BUILD 330 void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback, 331 bsp_clock_update_callback_args_t * p_callback_memory); 332 333 #endif 334 335 /* Used internally by CGC */ 336 337 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE 338 void bsp_prv_operating_mode_set(uint8_t operating_mode); 339 340 #endif 341 342 #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED 343 uint32_t bsp_prv_power_change_mstp_set(void); 344 void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); 345 346 #endif 347 348 void bsp_prv_prepare_pll(uint32_t pll_freq_hz); 349 void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr); 350 351 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 352 FSP_FOOTER 353 354 #endif 355