1 /***********************************************************************************************************************
2 * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
3 *
4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
19 **********************************************************************************************************************/
20
21 /***********************************************************************************************************************
22 * Includes <System Includes> , "Project Includes"
23 **********************************************************************************************************************/
24 #include "bsp_clocks.h"
25
26 #if BSP_TZ_NONSECURE_BUILD
27 #include "bsp_guard.h"
28 #endif
29
30 /***********************************************************************************************************************
31 * Macro definitions
32 **********************************************************************************************************************/
33
34 /* Key code for writing PRCR register. */
35 #define BSP_PRV_PRCR_KEY (0xA500U)
36 #define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U)
37 #define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
38
39 #define BSP_PRV_MAXIMUM_HOCOWTR_HSTS ((uint8_t) 0x6U)
40
41 /* Wait state definitions for MEMWAIT. */
42 #define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U)
43 #define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES (1U)
44 #define BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ (32000000U)
45
46 /* Wait state definitions for FLDWAITR. */
47 #define BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES (0U)
48 #define BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES (1U)
49 #define BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ (32000000U)
50
51 /* Temporary solution until R_FACI is added to renesas.h. */
52 #define BSP_PRV_FLDWAITR_REG_ACCESS (*((volatile uint8_t *) (0x407EFFC4U)))
53
54 /* Wait state definitions for MCUS with SRAMWTSC and FLWT. */
55 #define BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE (0U)
56 #define BSP_PRV_ROM_ZERO_WAIT_CYCLES (0U)
57 #define BSP_PRV_ROM_ONE_WAIT_CYCLES (1U)
58 #define BSP_PRV_ROM_TWO_WAIT_CYCLES (2U)
59 #define BSP_PRV_ROM_THREE_WAIT_CYCLES (3U)
60 #define BSP_PRV_SRAM_PRCR_KEY (0x78U)
61 #define BSP_PRV_SRAM_UNLOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x1U)
62 #define BSP_PRV_SRAM_LOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x0U)
63
64 /* Calculate value to write to MOMCR (MODRV controls main clock drive strength and MOSEL determines the source of the
65 * main oscillator). */
66 #define BSP_PRV_MOMCR_MOSEL_BIT (6)
67 #define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \
68 BSP_FEATURE_CGC_MODRV_MASK)
69 #define BSP_PRV_MOSEL (BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE << BSP_PRV_MOMCR_MOSEL_BIT)
70 #define BSP_PRV_MOMCR (BSP_PRV_MODRV | BSP_PRV_MOSEL)
71
72 /* Locations of bitfields used to configure CLKOUT. */
73 #define BSP_PRV_CKOCR_CKODIV_BIT (4U)
74 #define BSP_PRV_CKOCR_CKOEN_BIT (7U)
75
76 /* Stop interval of at least 5 SOSC clock cycles between stop and restart of SOSC.
77 * Calculated based on 8Mhz of MOCO clock. */
78 #define BSP_PRV_SUBCLOCK_STOP_INTERVAL_US (1220U)
79
80 #ifdef BSP_CFG_UCK_DIV
81
82 /* If the MCU has SCKDIVCR2. */
83 #if !BSP_FEATURE_BSP_HAS_USBCKDIVCR
84
85 /* Location of bitfield used to configure USB clock divider. */
86 #define BSP_PRV_SCKDIVCR2_UCK_BIT (4U)
87 #define BSP_PRV_UCK_DIV (BSP_CFG_UCK_DIV)
88
89 /* If the MCU has USBCKDIVCR. */
90 #elif BSP_FEATURE_BSP_HAS_USBCKDIVCR
91
92 #if BSP_CLOCKS_USB_CLOCK_DIV_3 == BSP_CFG_UCK_DIV
93 #define BSP_PRV_UCK_DIV (5U)
94 #elif BSP_CLOCKS_USB_CLOCK_DIV_4 == BSP_CFG_UCK_DIV
95 #define BSP_PRV_UCK_DIV (2U)
96 #elif BSP_CLOCKS_USB_CLOCK_DIV_5 == BSP_CFG_UCK_DIV
97 #define BSP_PRV_UCK_DIV (6U)
98 #else
99
100 #error "BSP_CFG_UCK_DIV not supported."
101
102 #endif
103 #endif
104 #endif
105
106 /* Choose the value to write to FLLCR2 (if applicable). */
107 #if BSP_PRV_HOCO_USE_FLL
108 #if 0U == BSP_CFG_HOCO_FREQUENCY
109 #define BSP_PRV_FLL_FLLCR2 (0x1E9U)
110 #elif 1U == BSP_CFG_HOCO_FREQUENCY
111 #define BSP_PRV_FLL_FLLCR2 (0x226U)
112 #elif 2U == BSP_CFG_HOCO_FREQUENCY
113 #define BSP_PRV_FLL_FLLCR2 (0x263U)
114 #endif
115 #endif
116
117 /* Calculate the value to write to SCKDIVCR. */
118 #define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 7U) << 24U)
119 #if BSP_FEATURE_CGC_HAS_PCLKD
120 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0x7U)
121 #else
122 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U)
123 #endif
124 #if BSP_FEATURE_CGC_HAS_PCLKC
125 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0x7U) << 4U)
126 #else
127 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U)
128 #endif
129 #if BSP_FEATURE_CGC_HAS_PCLKB
130 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U)
131 #else
132 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U)
133 #endif
134 #if BSP_FEATURE_CGC_HAS_PCLKA
135 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U)
136 #else
137 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U)
138 #endif
139 #if BSP_FEATURE_CGC_HAS_BCLK
140 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0x7U) << 16U)
141 #elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB
142
143 /* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */
144 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U)
145 #else
146 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U)
147 #endif
148 #if BSP_FEATURE_CGC_HAS_FCLK
149 #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0x7U) << 28U)
150 #else
151 #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U)
152 #endif
153 #define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \
154 BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \
155 BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \
156 BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \
157 BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \
158 BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \
159 BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS)
160
161 /* The number of clocks is used to size the g_clock_freq array. */
162 #if BSP_PRV_PLL2_SUPPORTED
163 #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + 1U)
164 #elif BSP_PRV_PLL_SUPPORTED
165 #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + 1U)
166 #else
167 #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U)
168 #endif
169
170 /* Calculate PLLCCR value. */
171 #if BSP_PRV_PLL_SUPPORTED
172 #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
173 #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
174 #define BSP_PRV_PLSRCSEL (0)
175 #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
176 #define BSP_PRV_PLSRCSEL (1)
177 #endif
178 #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x3F) // PLLMUL in PLLCCR is 6 bits wide
179 #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8
180 #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4
181 #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
182 BSP_PRV_PLLCCR_PLLMUL_BIT) | \
183 (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \
184 BSP_CFG_PLL_DIV)
185 #endif
186 #if (2U == BSP_FEATURE_CGC_PLLCCR_TYPE)
187 #define BSP_PRV_PLLCCR2_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR2 is 5 bits wide
188 #define BSP_PRV_PLLCCR2_PLODIV_BIT (6) // PLODIV in PLLCCR2 starts at bit 6
189
190 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
191 #define BSP_PRV_PLLCCR (BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \
192 (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT)
193 #endif
194 #endif
195
196 #if BSP_FEATURE_CGC_HAS_PLL2
197 #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE
198 #define BSP_PRV_PL2SRCSEL (0)
199 #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE
200 #define BSP_PRV_PL2SRCSEL (1)
201 #endif
202 #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \
203 (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
204 (BSP_PRV_PL2SRCSEL << R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos))
205 #endif
206
207 /* All clocks with configurable source except PLL and CLKOUT can use PLL. */
208 #if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
209 #define BSP_PRV_PLL_USED (1)
210 #define BSP_PRV_STABILIZE_PLL (1)
211 #elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
212 (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
213 #define BSP_PRV_PLL_USED (1)
214 #elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
215 #define BSP_PRV_PLL_USED (1)
216 #elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
217 #define BSP_PRV_PLL_USED (1)
218 #elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
219 #define BSP_PRV_PLL_USED (1)
220 #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
221 #define BSP_PRV_PLL_USED (1)
222 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
223 #define BSP_PRV_PLL_USED (1)
224 #else
225 #define BSP_PRV_PLL_USED (0)
226 #endif
227
228 /* All clocks with configurable source except the main clock, PLL, and CLKOUT can use PLL2. */
229 #if defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
230 (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
231 #define BSP_PRV_PLL2_USED (1)
232 #elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
233 #define BSP_PRV_PLL2_USED (1)
234 #elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
235 #define BSP_PRV_PLL2_USED (1)
236 #elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
237 #define BSP_PRV_PLL2_USED (1)
238 #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
239 #define BSP_PRV_PLL2_USED (1)
240 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
241 #define BSP_PRV_PLL2_USED (1)
242 #else
243 #define BSP_PRV_PLL2_USED (0)
244 #endif
245
246 /* All clocks with configurable source except UCK, CANFD can use the main oscillator. */
247 #if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
248 #define BSP_PRV_MAIN_OSC_USED (1)
249 #define BSP_PRV_STABILIZE_MAIN_OSC (1)
250 #elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL_USED
251 #define BSP_PRV_MAIN_OSC_USED (1)
252 #define BSP_PRV_STABILIZE_MAIN_OSC (1)
253 #elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL2_USED
254 #define BSP_PRV_MAIN_OSC_USED (1)
255 #define BSP_PRV_STABILIZE_MAIN_OSC (1)
256 #elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
257 #define BSP_PRV_MAIN_OSC_USED (1)
258 #elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
259 #define BSP_PRV_MAIN_OSC_USED (1)
260 #elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
261 #define BSP_PRV_MAIN_OSC_USED (1)
262 #elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
263 #define BSP_PRV_MAIN_OSC_USED (1)
264 #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
265 #define BSP_PRV_MAIN_OSC_USED (1)
266 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
267 #define BSP_PRV_MAIN_OSC_USED (1)
268 #else
269 #define BSP_PRV_MAIN_OSC_USED (0)
270 #endif
271
272 /* All clocks with configurable source can use HOCO. */
273 #if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
274 #define BSP_PRV_HOCO_USED (1)
275 #define BSP_PRV_STABILIZE_HOCO (1)
276 #elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL_USED
277 #define BSP_PRV_HOCO_USED (1)
278 #define BSP_PRV_STABILIZE_HOCO (1)
279 #elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL2_USED
280 #define BSP_PRV_HOCO_USED (1)
281 #define BSP_PRV_STABILIZE_HOCO (1)
282 #elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
283 (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
284 #define BSP_PRV_HOCO_USED (1)
285 #elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
286 #define BSP_PRV_HOCO_USED (1)
287 #elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
288 #define BSP_PRV_HOCO_USED (1)
289 #elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
290 #define BSP_PRV_HOCO_USED (1)
291 #elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
292 #define BSP_PRV_HOCO_USED (1)
293 #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
294 #define BSP_PRV_HOCO_USED (1)
295 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
296 #define BSP_PRV_HOCO_USED (1)
297 #else
298 #define BSP_PRV_HOCO_USED (0)
299 #endif
300
301 /* All clocks with configurable source except UCK, CANFD, and PLL can use MOCO. */
302 #if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
303 #define BSP_PRV_MOCO_USED (1)
304 #define BSP_PRV_STABILIZE_MOCO (1)
305 #elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
306 #define BSP_PRV_MOCO_USED (1)
307 #elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
308 #define BSP_PRV_MOCO_USED (1)
309 #elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
310 #define BSP_PRV_MOCO_USED (1)
311 #elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
312 #define BSP_PRV_MOCO_USED (1)
313 #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
314 #define BSP_PRV_MOCO_USED (1)
315 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
316 #define BSP_PRV_MOCO_USED (1)
317 #else
318 #define BSP_PRV_MOCO_USED (0)
319 #endif
320
321 /* All clocks with configurable source except UCK, CANFD, and PLL can use LOCO. */
322 #if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
323 #define BSP_PRV_LOCO_USED (1)
324 #define BSP_PRV_STABILIZE_LOCO (1)
325 #elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
326 #define BSP_PRV_LOCO_USED (1)
327 #elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
328 #define BSP_PRV_LOCO_USED (1)
329 #elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
330 #define BSP_PRV_LOCO_USED (1)
331 #elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
332 #define BSP_PRV_LOCO_USED (1)
333 #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
334 #define BSP_PRV_LOCO_USED (1)
335 #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
336 #define BSP_PRV_LOCO_USED (1)
337 #else
338 #define BSP_PRV_LOCO_USED (0)
339 #endif
340
341 /* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock
342 * frequency. */
343 #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && \
344 !BSP_PRV_PLL_USED && !BSP_PRV_PLL2_USED
345 #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_LOW_SPEED)
346 #elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ
347 #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED)
348 #else
349 #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_HIGH_SPEED)
350 #endif
351
352 #if BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB
353 #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0 == BSP_CFG_ROM_REG_OFS1_ICSATS)
354 #else
355 #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0)
356 #endif
357
358 /***********************************************************************************************************************
359 * Typedef definitions
360 **********************************************************************************************************************/
361
362 /***********************************************************************************************************************
363 * Exported global variables (to be accessed by other files)
364 **********************************************************************************************************************/
365
366 /***********************************************************************************************************************
367 * Private global variables and functions
368 **********************************************************************************************************************/
369 static uint8_t bsp_clock_set_prechange(uint32_t requested_freq_hz);
370 static void bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_rom_wait_state);
371
372 #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
373 #if defined(__ICCARM__)
374
375 void R_BSP_SubClockStabilizeWait(uint32_t delay_ms);
376
377 #pragma weak R_BSP_SubClockStabilizeWait
378
379 #elif defined(__GNUC__) || defined(__ARMCC_VERSION)
380
381 void R_BSP_SubClockStabilizeWait(uint32_t delay_ms) __attribute__((weak));
382
383 #endif
384 #endif
385
386 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE
387 static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode);
388
389 #endif
390
391 #if !BSP_CFG_SOFT_RESET_SUPPORTED
392 static void bsp_prv_clock_set_hard_reset(void);
393
394 #endif
395
396 /* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C
397 * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime
398 * environment is initialized. */
399 static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT);
400
401 #if BSP_TZ_SECURE_BUILD
402
403 /* Callback used to notify the nonsecure project that the clock settings have changed. */
404 static bsp_clock_update_callback_t g_bsp_clock_update_callback = NULL;
405
406 /* Pointer to nonsecure memory to store the callback args. */
407 static bsp_clock_update_callback_args_t * gp_callback_memory = NULL;
408
409 /* Reentrant method of calling the clock_update_callback. */
r_bsp_clock_update_callback_call(bsp_clock_update_callback_t p_callback,bsp_clock_update_callback_args_t * p_callback_args)410 static void r_bsp_clock_update_callback_call (bsp_clock_update_callback_t p_callback,
411 bsp_clock_update_callback_args_t * p_callback_args)
412 {
413 /* Allocate memory for saving global callback args on the secure stack. */
414 bsp_clock_update_callback_args_t callback_args;
415
416 /* Save current info stored in callback memory. */
417 callback_args = *gp_callback_memory;
418
419 /* Write the callback args to the nonsecure callback memory. */
420 *gp_callback_memory = *p_callback_args;
421
422 /* Call the callback to notifiy ns project about clock changes. */
423 p_callback(gp_callback_memory);
424
425 /* Restore the info in callback memory. */
426 *gp_callback_memory = callback_args;
427 }
428
429 /* Initialize the callback, callback memory and invoke the callback to ensure the nonsecure project has the correct clock settings. */
r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback,bsp_clock_update_callback_args_t * p_callback_memory)430 void r_bsp_clock_update_callback_set (bsp_clock_update_callback_t p_callback,
431 bsp_clock_update_callback_args_t * p_callback_memory)
432 {
433 /* Store pointer to nonsecure callback memory. */
434 gp_callback_memory = p_callback_memory;
435
436 /* Store callback. */
437 g_bsp_clock_update_callback = p_callback;
438
439 /* Set callback args. */
440 bsp_clock_update_callback_args_t callback_args =
441 {
442 .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL]
443 };
444
445 /* Call the callback. */
446 r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args);
447 }
448
449 #elif BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU
450
451 bsp_clock_update_callback_args_t g_callback_memory;
452 #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD
453 #if defined(__ARMCC_VERSION) || defined(__ICCARM__)
g_bsp_clock_update_callback(bsp_clock_update_callback_args_t * p_callback_args)454 static void BSP_CMSE_NONSECURE_CALL g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args)
455 #elif defined(__GNUC__)
456
457 static BSP_CMSE_NONSECURE_CALL void g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args)
458 #endif
459
460 {
461 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = p_callback_args->pll_freq;
462
463 /* Update the SystemCoreClock value based on the new g_clock_freq settings. */
464 SystemCoreClockUpdate();
465 }
466
467 #endif
468 #endif
469
470 #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
471
472 /* List of MSTP bits that must be set before entering low power modes or changing SCKDIVCR. */
473 static const uint8_t g_bsp_prv_power_change_mstp_data[][2] = BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY;
474
475 static const uint8_t g_bsp_prv_power_change_mstp_length = sizeof(g_bsp_prv_power_change_mstp_data) /
476 sizeof(g_bsp_prv_power_change_mstp_data[0]);
477
478 static volatile uint32_t * const gp_bsp_prv_mstp = &R_MSTP->MSTPCRB;
479 #endif
480
481 /*******************************************************************************************************************//**
482 * @internal
483 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
484 * @ingroup RENESAS_INTERNAL
485 * @{
486 **********************************************************************************************************************/
487
488 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE
489
490 /***********************************************************************************************************************
491 * Changes the operating speed in OPCCR. Assumes the LPM registers are unlocked in PRCR and cache is off.
492 *
493 * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros, cannot be
494 * BSP_PRV_OPERATING_MODE_SUBOSC_SPEED
495 **********************************************************************************************************************/
bsp_prv_operating_mode_opccr_set(uint8_t operating_mode)496 static void bsp_prv_operating_mode_opccr_set (uint8_t operating_mode)
497 {
498 #if BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR
499
500 /* If the desired operating mode is already set, return. */
501 if (operating_mode == R_SYSTEM->OPCCR)
502 {
503 return;
504 }
505
506 /* On some MCUs, the HOCO must be stable before updating OPCCR.OPCM. */
507 if (0U == R_SYSTEM->HOCOCR)
508 {
509 /* Wait for HOCO to stabilize. */
510 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
511 }
512 #endif
513
514 /* Wait for transition to complete. */
515 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U);
516
517 /* Apply requested operating speed mode. */
518 R_SYSTEM->OPCCR = operating_mode;
519
520 /* Wait for transition to complete. */
521 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U);
522 }
523
524 #endif
525
526 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE
527
528 /***********************************************************************************************************************
529 * Changes the operating speed mode. Assumes the LPM registers are unlocked in PRCR and cache is off.
530 *
531 * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros
532 **********************************************************************************************************************/
bsp_prv_operating_mode_set(uint8_t operating_mode)533 void bsp_prv_operating_mode_set (uint8_t operating_mode)
534 {
535 #if BSP_PRV_POWER_USE_DCDC
536 static bsp_power_mode_t power_mode = BSP_POWER_MODE_LDO;
537
538 /* Disable DCDC if transitioning to an incompatible mode. */
539 if ((operating_mode > BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk))
540 {
541 /* LDO boost must be used if entering subclock speed mode (see RA2L1 User's Manual (R01UH0853EJ0100) Section
542 * 10.5.1 (5) Switching from High-speed/Middle-speed mode in DCDC power mode to Subosc-speed mode or Software
543 * Standby mode). */
544 power_mode = R_BSP_PowerModeSet((BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) ?
545 BSP_POWER_MODE_LDO_BOOST : BSP_POWER_MODE_LDO);
546 }
547 #endif
548
549 if (BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode)
550 {
551 /* Wait for transition to complete. */
552 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
553
554 /* Set subosc speed mode. */
555 R_SYSTEM->SOPCCR = 0x1U;
556
557 /* Wait for transition to complete. */
558 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
559 }
560 else
561 {
562 /* Wait for transition to complete. */
563 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
564
565 /* Exit subosc speed mode first. */
566 R_SYSTEM->SOPCCR = 0U;
567
568 /* Wait for transition to complete. Check the entire register here since it should be set to 0 at this point.
569 * Checking the entire register is slightly more efficient. This will also hang the program if the LPM
570 * registers are not unlocked, which can help catch programming errors. */
571 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR, 0U);
572
573 bsp_prv_operating_mode_opccr_set(operating_mode);
574 }
575
576 #if BSP_PRV_POWER_USE_DCDC
577
578 /* Enable DCDC if it was previously enabled. */
579 if ((operating_mode <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (power_mode < BSP_POWER_MODE_LDO))
580 {
581 R_BSP_PowerModeSet(power_mode);
582 power_mode = BSP_POWER_MODE_LDO;
583 }
584 #endif
585 }
586
587 #endif
588
589 #if BSP_PRV_PLL_SUPPORTED
590
591 /***********************************************************************************************************************
592 * Updates the operating frequency of the PLL.
593 *
594 * @param[in] pll_freq_hz New frequency of the PLL after the PLL is configured
595 **********************************************************************************************************************/
bsp_prv_prepare_pll(uint32_t pll_freq_hz)596 void bsp_prv_prepare_pll (uint32_t pll_freq_hz)
597 {
598 /* Store the PLL frequency, which is required to update SystemCoreClock after switching to PLL. */
599 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = pll_freq_hz;
600 }
601
602 #endif
603
604 /*******************************************************************************************************************//**
605 * Update SystemCoreClock variable based on current clock settings.
606 **********************************************************************************************************************/
SystemCoreClockUpdate(void)607 void SystemCoreClockUpdate (void)
608 {
609 uint32_t clock_index = R_SYSTEM->SCKSCR;
610 SystemCoreClock = g_clock_freq[clock_index] >> R_SYSTEM->SCKDIVCR_b.ICK;
611 }
612
613 #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
614
615 /*******************************************************************************************************************//**
616 * Sets MSTP bits as required by the hardware manual for the MCU (reference Figure 9.2 "Example flow for changing the
617 * value of SCKDIVCR" in the RA6M3 manual R01UH0886EJ0100).
618 *
619 * This function must be called before entering standby or changing SCKDIVCR.
620 *
621 * @return bitmask of bits set, where each bit corresponds to an index in g_bsp_prv_power_change_mstp_data
622 **********************************************************************************************************************/
bsp_prv_power_change_mstp_set(void)623 uint32_t bsp_prv_power_change_mstp_set (void)
624 {
625 uint32_t mstp_set_bitmask = 0U;
626 for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++)
627 {
628 /* Get the MSTP register index and the bit to test from the MCU specific array. */
629 uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0];
630 uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1];
631
632 /* Only set the bit if it's currently cleared. */
633 if (!(gp_bsp_prv_mstp[mstp_index] & mstp_bit))
634 {
635 gp_bsp_prv_mstp[mstp_index] |= mstp_bit;
636 mstp_set_bitmask |= 1U << i;
637 }
638
639 /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being set. It was measured
640 * at 58 cycles for default IAR build configurations and 59 cycles for default GCC build configurations. */
641 }
642
643 /* The time between setting last MSTP bit and setting SCKDIVCR takes over 750 ns (90 cycles at 120 MHz). It was
644 * measured at 96 cycles for default IAR build configurations and 102 cycles for default GCC build
645 * configurations. */
646
647 return mstp_set_bitmask;
648 }
649
650 #endif
651
652 #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
653
654 /*******************************************************************************************************************//**
655 * Clears MSTP bits set by bsp_prv_power_change_mstp_set as required by the hardware manual for the MCU (reference
656 * Figure 9.2 "Example flow for changing the value of SCKDIVCR" in the RA6M3 manual R01UH0886EJ0100).
657 *
658 * This function must be called after exiting standby or changing SCKDIVCR.
659 *
660 * @param[in] mstp_clear_bitmask bitmask of bits to clear, where each bit corresponds to an index in
661 * g_bsp_prv_power_change_mstp_data
662 **********************************************************************************************************************/
bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask)663 void bsp_prv_power_change_mstp_clear (uint32_t mstp_clear_bitmask)
664 {
665 /* The time between setting SCKDIVCR and clearing the first MSTP bit takes over 250 ns (30 cycles at 120 MHz). It
666 * was measured at 38 cycles for default IAR build configurations and 68 cycles for default GCC build
667 * configurations. */
668
669 for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++)
670 {
671 /* Only clear the bit if it was set in bsp_prv_power_change_mstp_set. */
672 if ((1U << i) & mstp_clear_bitmask)
673 {
674 /* Get the MSTP register index and the bit to test from the MCU specific array. */
675 uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0];
676 uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1];
677
678 gp_bsp_prv_mstp[mstp_index] &= ~mstp_bit;
679 }
680
681 /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being cleared. It was measured
682 * at 44 cycles for default IAR build configurations and 53 cycles for default GCC build configurations. */
683 }
684 }
685
686 #endif
687
688 /*******************************************************************************************************************//**
689 * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this
690 * configuration and the CGC registers are expected to be unlocked in PRCR.
691 *
692 * @param[in] clock Desired system clock
693 * @param[in] sckdivcr Value to set in SCKDIVCR register
694 **********************************************************************************************************************/
bsp_prv_clock_set(uint32_t clock,uint32_t sckdivcr)695 void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr)
696 {
697 #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
698
699 /* Set MSTP bits as required by the hardware manual. This is done first to ensure the 750 ns delay required after
700 * increasing any division ratio in SCKDIVCR is met. */
701 uint32_t mstp_set_bitmask = bsp_prv_power_change_mstp_set();
702 #endif
703
704 uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK;
705
706 /* Adjust the MCU specific wait state right before the system clock is set, if the system clock frequency to be
707 * set is higher than before. */
708 uint32_t clock_freq_hz_post_change = g_clock_freq[clock] >> iclk_div;
709 uint8_t new_rom_wait_state = bsp_clock_set_prechange(clock_freq_hz_post_change);
710
711 /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and
712 * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */
713
714 /* If the current ICLK divider is less (higher frequency) than the requested ICLK divider, set the divider
715 * first. */
716 sckdivcr = sckdivcr & BSP_PRV_SCKDIVCR_MASK;
717 if (R_SYSTEM->SCKDIVCR_b.ICK < iclk_div)
718 {
719 /* Set the system dividers */
720 R_SYSTEM->SCKDIVCR = sckdivcr;
721
722 /* Set the system source clock */
723 R_SYSTEM->SCKSCR = (uint8_t) clock;
724 }
725 /* If the current ICLK divider is greater (lower frequency) than the requested ICLK divider, set the clock
726 * source first. If the ICLK divider is the same, order does not matter. */
727 else
728 {
729 /* Set the system source clock */
730 R_SYSTEM->SCKSCR = (uint8_t) clock;
731
732 /* Set the system dividers */
733 R_SYSTEM->SCKDIVCR = sckdivcr;
734 }
735
736 /* Clock is now at requested frequency. */
737
738 /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
739 SystemCoreClock = clock_freq_hz_post_change;
740
741 #if BSP_TZ_SECURE_BUILD
742 if (NULL != g_bsp_clock_update_callback)
743 {
744 /* Set callback args. */
745 bsp_clock_update_callback_args_t callback_args =
746 {
747 .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL]
748 };
749
750 /* Call the callback. */
751 r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args);
752 }
753 #endif
754
755 /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be
756 * set is lower than previous. */
757 bsp_clock_set_postchange(SystemCoreClock, new_rom_wait_state);
758
759 #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
760
761 /* Clear MSTP bits as required by the hardware manual. This is done last to ensure the 250 ns delay required after
762 * decreasing any division ratio in SCKDIVCR is met. */
763 bsp_prv_power_change_mstp_clear(mstp_set_bitmask);
764 #endif
765 }
766
767 #if !BSP_CFG_SOFT_RESET_SUPPORTED
768
bsp_prv_clock_set_hard_reset(void)769 static void bsp_prv_clock_set_hard_reset (void)
770 {
771 /* Wait states in SRAMWTSC are set after hard reset. No change required here. */
772
773 /* Calculate the wait states for ROM */
774 #if BSP_FEATURE_CGC_HAS_FLWT
775 #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS
776
777 /* Do nothing. Default setting in FLWT is correct. */
778 #elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS || \
779 BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS == 0
780 R_FCACHE->FLWT = BSP_PRV_ROM_ONE_WAIT_CYCLES;
781 #elif 0 == BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS || \
782 (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS)
783 R_FCACHE->FLWT = BSP_PRV_ROM_TWO_WAIT_CYCLES;
784 #else
785 R_FCACHE->FLWT = BSP_PRV_ROM_THREE_WAIT_CYCLES;
786 #endif
787 #endif
788
789 #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B
790 #if BSP_STARTUP_ICLK_HZ > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ
791
792 /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */
793 R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES;
794 #endif
795 #endif
796
797 #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B
798 #if BSP_STARTUP_ICLK_HZ > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ
799
800 /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */
801 BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES;
802 #endif
803 #endif
804
805 /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and
806 * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */
807
808 /* ICLK divider at reset is lowest possible, so set dividers first. */
809
810 /* Set the system dividers first if ICLK divisor is larger than reset value. */
811 #if BSP_CFG_ICLK_DIV >= BSP_FEATURE_CGC_ICLK_DIV_RESET
812 R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
813 #endif
814
815 /* Set the system source clock */
816 R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE;
817
818 /* Set the system dividers after setting the system clock source if ICLK divisor is smaller than reset value. */
819 #if BSP_CFG_ICLK_DIV < BSP_FEATURE_CGC_ICLK_DIV_RESET
820 R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
821 #endif
822
823 /* Clock is now at requested frequency. */
824
825 /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
826 SystemCoreClockUpdate();
827
828 /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be
829 * set is lower than previous. */
830 #if BSP_FEATURE_CGC_HAS_SRAMWTSC
831 #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS
832 #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1
833 R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK;
834 R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE;
835 R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK;
836 #else
837 R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
838 R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE;
839 R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
840 #endif
841 #endif
842 #endif
843
844 /* ROM wait states are 0 by default. No change required here. */
845 }
846
847 #endif
848
849 /*******************************************************************************************************************//**
850 * Initializes variable to store system clock frequencies.
851 **********************************************************************************************************************/
852 #if BSP_TZ_NONSECURE_BUILD
bsp_clock_freq_var_init(void)853 void bsp_clock_freq_var_init (void)
854 #else
855 static void bsp_clock_freq_var_init (void)
856 #endif
857 {
858 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] = BSP_HOCO_HZ;
859 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO] = BSP_MOCO_FREQ_HZ;
860 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO] = BSP_LOCO_FREQ_HZ;
861 #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED
862 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = BSP_CFG_XTAL_HZ;
863 #else
864 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = 0U;
865 #endif
866 #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
867 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = BSP_SUBCLOCK_FREQ_HZ;
868 #else
869 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = 0U;
870 #endif
871 #if BSP_PRV_PLL_SUPPORTED
872 #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
873
874 /* The PLL Is the startup clock. */
875 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ;
876 #else
877
878 /* The PLL value will be calculated at initialization. */
879 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_XTAL_HZ;
880 #endif
881 #endif
882
883 #if BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU
884
885 /* If the CGC is secure and this is a non secure project, register a callback for getting clock settings. */
886 R_BSP_ClockUpdateCallbackSet(g_bsp_clock_update_callback, &g_callback_memory);
887 #endif
888
889 /* Update PLL Clock Frequency based on BSP Configuration. */
890 #if BSP_PRV_PLL_SUPPORTED && BSP_CLOCKS_SOURCE_CLOCK_PLL != BSP_CFG_CLOCK_SOURCE && BSP_PRV_PLL_USED
891 #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
892 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) /
893 (BSP_CFG_PLL_DIV + 1U);
894 #else
895 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >>
896 BSP_CFG_PLL_DIV;
897 #endif
898 #endif
899
900 /* Update PLL2 Clock Frequency based on BSP Configuration. */
901 #if BSP_PRV_PLL2_SUPPORTED && BSP_PRV_PLL2_USED
902 #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
903 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) /
904 (BSP_CFG_PLL2_DIV + 1U);
905 #else
906 g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] =
907 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV;
908 #endif
909 #endif
910
911 /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */
912 SystemCoreClockUpdate();
913 }
914
915 /*******************************************************************************************************************//**
916 * Initializes system clocks. Makes no assumptions about current register settings.
917 **********************************************************************************************************************/
bsp_clock_init(void)918 void bsp_clock_init (void)
919 {
920 /* Unlock CGC and LPM protection registers. */
921 R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK;
922
923 #if BSP_FEATURE_BSP_FLASH_CACHE
924 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM
925
926 /* Disable flash cache before modifying MEMWAIT, SOPCCR, or OPCCR. */
927 R_BSP_FlashCacheDisable();
928 #else
929
930 /* Enable the flash cache and don't disable it while running from flash. On these MCUs, the flash cache does not
931 * need to be disabled when adjusting the operating power mode. */
932 R_BSP_FlashCacheEnable();
933 #endif
934 #endif
935
936 #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER
937
938 /* Disable the flash prefetch buffer. */
939 R_FACI_LP->PFBER = 0;
940 #endif
941
942 bsp_clock_freq_var_init();
943
944 #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED
945 #if BSP_CFG_SOFT_RESET_SUPPORTED
946
947 /* Update the main oscillator drive, source, and wait states if the main oscillator is stopped. If the main
948 * oscillator is running, the drive, source, and wait states are assumed to be already set appropriately. */
949 if (R_SYSTEM->MOSCCR)
950 {
951 /* Don't write to MOSCWTCR unless MOSTP is 1 and MOSCSF = 0. */
952 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 0U);
953
954 /* Configure main oscillator drive. */
955 R_SYSTEM->MOMCR = BSP_PRV_MOMCR;
956
957 /* Set the main oscillator wait time. */
958 R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT;
959 }
960
961 #else
962
963 /* Configure main oscillator drive. */
964 R_SYSTEM->MOMCR = BSP_PRV_MOMCR;
965
966 /* Set the main oscillator wait time. */
967 R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT;
968 #endif
969 #endif
970
971 #if BSP_FEATURE_CGC_HAS_SOSC
972 #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
973
974 /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */
975 if (0U == R_SYSTEM->SOSCCR)
976 {
977 /* Stop the Sub-Clock Oscillator to update the SOMCR register. */
978 R_SYSTEM->SOSCCR = 1U;
979
980 /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity
981 * and restarting Sub-Clock Oscillator. */
982 R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS);
983 }
984
985 /* Configure the subclock drive as subclock is not running. */
986 R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK);
987
988 /* Restart the Sub-Clock Oscillator. */
989 R_SYSTEM->SOSCCR = 0U;
990 #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)
991
992 /* If the subclock is the system clock source OR if FLL is used, wait for stabilization. */
993 R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS);
994 #endif
995 #else
996 R_SYSTEM->SOSCCR = 1U;
997 #endif
998 #endif
999
1000 #if BSP_FEATURE_CGC_HAS_HOCOWTCR
1001 #if BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY
1002
1003 /* These MCUs only require writes to HOCOWTCR if HOCO is set to 64 MHz. */
1004 #if 64000000 == BSP_HOCO_HZ
1005 #if BSP_CFG_USE_LOW_VOLTAGE_MODE
1006
1007 /* Wait for HOCO to stabilize before writing to HOCOWTCR. */
1008 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
1009 #else
1010
1011 /* HOCO is assumed to be stable because these MCUs also require the HOCO to be stable before changing the operating
1012 * power control mode. */
1013 #endif
1014 R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS;
1015 #endif
1016 #else
1017
1018 /* These MCUs require HOCOWTCR to be set to the maximum value except in snooze mode. There is no restriction to
1019 * writing this register. */
1020 R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS;
1021 #endif
1022 #endif
1023
1024 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE
1025 #if BSP_CFG_SOFT_RESET_SUPPORTED
1026
1027 /* Switch to high-speed to prevent any issues with the subsequent clock configurations. */
1028 bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED);
1029 #elif BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ > 0U
1030
1031 /* MCUs that support low voltage mode start up in low voltage mode. */
1032 bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED);
1033
1034 #if !BSP_PRV_HOCO_USED
1035
1036 /* HOCO must be running during startup in low voltage mode. If HOCO is not used, turn it off after exiting low
1037 * voltage mode. */
1038 R_SYSTEM->HOCOCR = 1U;
1039 #endif
1040 #elif BSP_FEATURE_CGC_STARTUP_OPCCR_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED
1041
1042 /* Some MCUs do not start in high speed mode. */
1043 bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED);
1044 #endif
1045 #endif
1046
1047 /* The FLL function can only be used when the subclock is running. */
1048 #if BSP_PRV_HOCO_USE_FLL
1049
1050 /* If FLL is to be used configure FLLCR1 and FLLCR2 before starting HOCO. */
1051 R_SYSTEM->FLLCR2 = BSP_PRV_FLL_FLLCR2;
1052 R_SYSTEM->FLLCR1 = 1U;
1053 #endif
1054
1055 /* Start all clocks used by other clocks first. */
1056 #if BSP_PRV_HOCO_USED
1057 R_SYSTEM->HOCOCR = 0U;
1058
1059 #if BSP_PRV_HOCO_USE_FLL && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE)
1060
1061 /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */
1062 R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS);
1063 #endif
1064
1065 #if BSP_PRV_STABILIZE_HOCO
1066
1067 /* Wait for HOCO to stabilize. */
1068 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
1069 #endif
1070 #endif
1071 #if BSP_PRV_MOCO_USED
1072 #if BSP_CFG_SOFT_RESET_SUPPORTED
1073
1074 /* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */
1075 if (0U != R_SYSTEM->MOCOCR)
1076 {
1077 R_SYSTEM->MOCOCR = 0U;
1078 #if BSP_PRV_STABILIZE_MOCO
1079 R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
1080 #endif
1081 }
1082 #endif
1083 #endif
1084 #if BSP_PRV_LOCO_USED
1085 #if BSP_CFG_SOFT_RESET_SUPPORTED
1086
1087 /* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */
1088 if (0U != R_SYSTEM->LOCOCR)
1089 {
1090 R_SYSTEM->LOCOCR = 0U;
1091 #if BSP_PRV_STABILIZE_LOCO
1092 R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
1093 #endif
1094 }
1095
1096 #else
1097 R_SYSTEM->LOCOCR = 0U;
1098 #if BSP_PRV_STABILIZE_LOCO
1099 R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
1100 #endif
1101 #endif
1102 #endif
1103 #if BSP_PRV_MAIN_OSC_USED
1104 R_SYSTEM->MOSCCR = 0U;
1105
1106 #if BSP_PRV_STABILIZE_MAIN_OSC
1107
1108 /* Wait for main oscillator to stabilize. */
1109 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U);
1110 #endif
1111 #endif
1112
1113 /* Start clocks that require other clocks. At this point, all dependent clocks are running and stable if needed. */
1114
1115 #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED
1116 #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED
1117 R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR;
1118
1119 /* Start PLL2. */
1120 R_SYSTEM->PLL2CR = 0U;
1121 #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */
1122 #endif
1123
1124 #if BSP_PRV_PLL_SUPPORTED && BSP_PRV_PLL_USED
1125 #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
1126
1127 /* Configure the PLL registers. */
1128 #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE
1129 R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR;
1130 #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE
1131 R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR;
1132 #endif
1133
1134 #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0
1135
1136 /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some
1137 * MCUs (see PLLSTP notes in Section 8.2.4 "PLL Control Register (PLLCR)" of the RA4M1 manual R01UH0887EJ0100).
1138 * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of
1139 * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running
1140 * while setting PLLCCR. */
1141 bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US));
1142 #endif
1143 #endif
1144
1145 R_SYSTEM->PLLCR = 0U;
1146
1147 #if BSP_PRV_STABILIZE_PLL
1148
1149 /* Wait for PLL to stabilize. */
1150 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U);
1151 #endif
1152 #endif
1153
1154 /* Set source clock and dividers. */
1155 #if BSP_CFG_SOFT_RESET_SUPPORTED
1156 #if BSP_TZ_SECURE_BUILD
1157
1158 /* In case of soft reset, make sure callback pointer is NULL initially. */
1159 g_bsp_clock_update_callback = NULL;
1160 #endif
1161
1162 bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR);
1163 #else
1164 bsp_prv_clock_set_hard_reset();
1165 #endif
1166
1167 /* If the MCU can run in a lower power mode, apply the optimal operating speed mode. */
1168 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE
1169 #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED
1170 #if BSP_PRV_PLL_SUPPORTED
1171 #if BSP_CFG_SOFT_RESET_SUPPORTED
1172 if (BSP_PRV_OPERATING_MODE_LOW_SPEED == BSP_PRV_STARTUP_OPERATING_MODE)
1173 {
1174 /* If the MCU has a PLL, ensure PLL is stopped and stable before entering low speed mode. */
1175 R_SYSTEM->PLLCR = 1U;
1176
1177 /* Wait for PLL to stabilize. */
1178 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0U);
1179
1180 #if BSP_FEATURE_CGC_HAS_PLL2
1181
1182 /* If the MCU has a PLL2, ensure PLL2 is stopped and stable before entering low speed mode. */
1183 R_SYSTEM->PLL2CR = 1U;
1184
1185 /* Wait for PLL to stabilize. */
1186 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 0U);
1187 #endif
1188 }
1189 #endif
1190 #endif
1191 bsp_prv_operating_mode_set(BSP_PRV_STARTUP_OPERATING_MODE);
1192 #endif
1193 #endif
1194
1195 #if defined(BSP_PRV_POWER_USE_DCDC) && (BSP_PRV_POWER_USE_DCDC == BSP_PRV_POWER_DCDC_STARTUP) && \
1196 (BSP_PRV_STARTUP_OPERATING_MODE <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED)
1197
1198 /* Start DCDC as part of BSP startup when configured (BSP_CFG_DCDC_ENABLE == 2). */
1199 R_BSP_PowerModeSet(BSP_CFG_DCDC_VOLTAGE_RANGE);
1200 #endif
1201
1202 /* Configure BCLK if it exists on the MCU. */
1203 #ifdef BSP_CFG_BCLK_OUTPUT
1204 #if BSP_CFG_BCLK_OUTPUT > 0U
1205 R_SYSTEM->BCKCR = BSP_CFG_BCLK_OUTPUT - 1U;
1206 R_SYSTEM->EBCKOCR = 1U;
1207 #else
1208 #if BSP_CFG_SOFT_RESET_SUPPORTED
1209 R_SYSTEM->EBCKOCR = 0U;
1210 #endif
1211 #endif
1212 #endif
1213
1214 /* Configure SDRAM clock if it exists on the MCU. */
1215 #ifdef BSP_CFG_SDCLK_OUTPUT
1216 R_SYSTEM->SDCKOCR = BSP_CFG_SDCLK_OUTPUT;
1217 #endif
1218
1219 /* Configure CLKOUT. */
1220 #if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED
1221 #if BSP_CFG_SOFT_RESET_SUPPORTED
1222 R_SYSTEM->CKOCR = 0U;
1223 #endif
1224 #else
1225 uint8_t ckocr = BSP_CFG_CLKOUT_SOURCE | (BSP_CFG_CLKOUT_DIV << BSP_PRV_CKOCR_CKODIV_BIT);
1226 R_SYSTEM->CKOCR = ckocr;
1227 ckocr |= (1U << BSP_PRV_CKOCR_CKOEN_BIT);
1228 R_SYSTEM->CKOCR = ckocr;
1229 #endif
1230
1231 #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED
1232 #if BSP_CFG_UCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED
1233
1234 /* If the USB clock has a divider setting in SCKDIVCR2. */
1235 #if BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV && !BSP_FEATURE_BSP_HAS_USBCKDIVCR
1236 R_SYSTEM->SCKDIVCR2 = BSP_PRV_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT;
1237 #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV && !BSP_FEATURE_BSP_HAS_USBCKDIVCR */
1238
1239 /* If there is a REQ bit in USBCKCR than follow sequence from section 8.2.29 in RA6M4 hardware manual R01UH0890EJ0050. */
1240 #if BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ
1241
1242 /* Request to change the USB Clock. */
1243 R_SYSTEM->USBCKCR_b.USBCKSREQ = 1;
1244
1245 /* Wait for the clock to be stopped. */
1246 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 1U);
1247
1248 /* Write the settings. */
1249 R_SYSTEM->USBCKDIVCR = BSP_PRV_UCK_DIV;
1250
1251 /* Select the USB Clock without enabling it. */
1252 R_SYSTEM->USBCKCR = BSP_CFG_UCK_SOURCE | R_SYSTEM_USBCKCR_USBCKSREQ_Msk;
1253 #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ */
1254
1255 #if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL
1256
1257 /* Some MCUs use an alternate register for selecting the USB clock source. */
1258 #if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT
1259 #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_UCK_SOURCE
1260
1261 /* Write to USBCKCR to select the PLL. */
1262 R_SYSTEM->USBCKCR_ALT = 0;
1263 #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_UCK_SOURCE
1264
1265 /* Write to USBCKCR to select the HOCO. */
1266 R_SYSTEM->USBCKCR_ALT = 1;
1267 #endif
1268 #else
1269
1270 /* Select the USB Clock. */
1271 R_SYSTEM->USBCKCR = BSP_CFG_UCK_SOURCE;
1272 #endif
1273 #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ */
1274
1275 #if BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ
1276
1277 /* Wait for the USB Clock to be started. */
1278 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 0U);
1279 #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ */
1280 #endif /* BSP_CFG_USB_ENABLE */
1281 #endif /* BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED */
1282
1283 /* Set the OCTASPI clock if it exists on the MCU (See section 8.2.30 of the RA6M4 hardware manual R01UH0890EJ0050). */
1284 #if BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK && BSP_CFG_OCTA_SOURCE != BSP_CLOCKS_CLOCK_DISABLED
1285 bsp_octaclk_settings_t octaclk_settings =
1286 {
1287 .source_clock = (bsp_clocks_source_t) BSP_CFG_OCTA_SOURCE,
1288 .divider = (bsp_clocks_octaclk_div_t) BSP_CFG_OCTA_DIV
1289 };
1290 R_BSP_OctaclkUpdate(&octaclk_settings);
1291 #endif /* BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK && BSP_CFG_OCTASPI_CLOCK_ENABLE */
1292
1293 /* Set the CANFD clock if it exists on the MCU */
1294 #if BSP_FEATURE_BSP_HAS_CANFD_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \
1295 (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
1296
1297 /* Request to stop the CANFD clock. */
1298 R_SYSTEM->CANFDCKCR_b.CANFDCKSREQ = 1;
1299
1300 /* Wait for the CANFD clock to stop. */
1301 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->CANFDCKCR_b.CANFDCKSRDY, 1U);
1302
1303 /* Select the CANFD clock divisor and source. */
1304 R_SYSTEM->CANFDCKDIVCR = BSP_CFG_CANFDCLK_DIV;
1305 R_SYSTEM->CANFDCKCR = BSP_CFG_CANFDCLK_SOURCE | R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk |
1306 R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk;
1307
1308 /* Request to start the CANFD clock. */
1309 R_SYSTEM->CANFDCKCR_b.CANFDCKSREQ = 0;
1310
1311 /* Wait for the CANFD clock to start. */
1312 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->CANFDCKCR_b.CANFDCKSRDY, 0U);
1313 #endif
1314
1315 /* Set the SCISPI clock if it exists on the MCU */
1316 #if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
1317
1318 /* Request to stop the SCISPI clock. */
1319 R_SYSTEM->SCISPICKCR_b.SCISPICKSREQ = 1;
1320
1321 /* Wait for the SCISPI clock to stop. */
1322 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SCISPICKCR_b.SCISPICKSRDY, 1U);
1323
1324 /* Select the SCISPI clock divisor and source. */
1325 R_SYSTEM->SCISPICKDIVCR = BSP_CFG_SCISPICLK_DIV;
1326 R_SYSTEM->SCISPICKCR = BSP_CFG_SCISPICLK_SOURCE | R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk |
1327 R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk;
1328
1329 /* Request to start the SCISPI clock. */
1330 R_SYSTEM->SCISPICKCR_b.SCISPICKSREQ = 0;
1331
1332 /* Wait for the SCISPI clock to start. */
1333 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SCISPICKCR_b.SCISPICKSRDY, 0U);
1334 #endif
1335
1336 /* Set the GPT clock if it exists on the MCU */
1337 #if BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
1338
1339 /* Request to stop the GPT clock. */
1340 R_SYSTEM->GPTCKCR_b.GPTCKSREQ = 1;
1341
1342 /* Wait for the GPT clock to stop. */
1343 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->GPTCKCR_b.GPTCKSRDY, 1U);
1344
1345 /* Select the GPT clock divisor and source. */
1346 R_SYSTEM->GPTCKDIVCR = BSP_CFG_GPTCLK_DIV;
1347 R_SYSTEM->GPTCKCR = BSP_CFG_GPTCLK_SOURCE | R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk |
1348 R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk;
1349
1350 /* Request to start the GPT clock. */
1351 R_SYSTEM->GPTCKCR_b.GPTCKSREQ = 0;
1352
1353 /* Wait for the GPT clock to start. */
1354 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->GPTCKCR_b.GPTCKSRDY, 0U);
1355 #endif
1356
1357 /* Set the IIC clock if it exists on the MCU */
1358 #if BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
1359
1360 /* Request to stop the IIC clock. */
1361 R_SYSTEM->IICCKCR_b.IICCKSREQ = 1;
1362
1363 /* Wait for the IIC clock to stop. */
1364 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->IICCKCR_b.IICCKSRDY, 1U);
1365
1366 /* Select the IIC clock divisor and source. */
1367 R_SYSTEM->IICCKDIVCR = BSP_CFG_IICCLK_DIV;
1368 R_SYSTEM->IICCKCR = BSP_CFG_IICCLK_SOURCE | R_SYSTEM_IICCKCR_IICCKSREQ_Msk |
1369 R_SYSTEM_IICCKCR_IICCKSRDY_Msk;
1370
1371 /* Request to start the IIC clock. */
1372 R_SYSTEM->IICCKCR_b.IICCKSREQ = 0;
1373
1374 /* Wait for the IIC clock to start. */
1375 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->IICCKCR_b.IICCKSRDY, 0U);
1376 #endif
1377
1378 /* Lock CGC and LPM protection registers. */
1379 R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
1380
1381 #if BSP_FEATURE_BSP_FLASH_CACHE && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM
1382 R_BSP_FlashCacheEnable();
1383 #endif
1384
1385 #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER
1386 R_FACI_LP->PFBER = 1;
1387 #endif
1388 }
1389
1390 #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
1391
1392 /*******************************************************************************************************************//**
1393 * This function is called during SOSC stabilization when Sub-Clock oscillator is populated.
1394 * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
1395 * implemented version. One of the main uses for this function is to update the IWDT/WDT Refresh Register if an
1396 * application starts IWDT/WDT automatically after reset. To use this function just copy this function into your own
1397 * code and modify it to meet your needs.
1398 *
1399 * @param[in] delay_ms Stabilization Time for the clock.
1400 **********************************************************************************************************************/
R_BSP_SubClockStabilizeWait(uint32_t delay_ms)1401 void R_BSP_SubClockStabilizeWait (uint32_t delay_ms)
1402 {
1403 /* Wait for clock to stabilize. */
1404 R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS);
1405 }
1406
1407 #endif
1408
1409 /*******************************************************************************************************************//**
1410 * Increases the ROM and RAM wait state settings to the minimum required based on the requested clock change.
1411 *
1412 * @param[in] requested_freq_hz New core clock frequency after the clock change.
1413 *
1414 * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist).
1415 **********************************************************************************************************************/
bsp_clock_set_prechange(uint32_t requested_freq_hz)1416 static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz)
1417 {
1418 uint8_t new_rom_wait_state = 0U;
1419
1420 FSP_PARAMETER_NOT_USED(requested_freq_hz);
1421
1422 #if BSP_FEATURE_CGC_HAS_SRAMWTSC
1423
1424 /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */
1425 if (requested_freq_hz > BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS)
1426 {
1427 #ifdef BSP_FEATURE_CGC_HAS_SRAMPRCR2
1428 R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK;
1429 R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE;
1430 R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK;
1431 #else
1432 R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
1433 R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE;
1434 R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
1435 #endif
1436 }
1437 #endif
1438
1439 #if BSP_FEATURE_CGC_HAS_FLWT
1440
1441 /* Calculate the wait states for ROM */
1442 #if BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS == 0
1443 if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS)
1444 {
1445 new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES;
1446 }
1447 else
1448 {
1449 new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES;
1450 }
1451
1452 #elif BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS == 0
1453 if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS)
1454 {
1455 new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES;
1456 }
1457 else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS)
1458 {
1459 new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES;
1460 }
1461 else
1462 {
1463 new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES;
1464 }
1465
1466 #else
1467 if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS)
1468 {
1469 new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES;
1470 }
1471 else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS)
1472 {
1473 new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES;
1474 }
1475 else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS)
1476 {
1477 new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES;
1478 }
1479 else
1480 {
1481 new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES;
1482 }
1483 #endif
1484
1485 /* If more wait states are required after the change, then set the wait states before changing the clock. */
1486 if (new_rom_wait_state > R_FCACHE->FLWT)
1487 {
1488 R_FCACHE->FLWT = new_rom_wait_state;
1489 }
1490 #endif
1491
1492 #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B
1493 if (requested_freq_hz > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ)
1494 {
1495 /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as
1496 * a precondition to bsp_prv_clock_set. */
1497 R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES;
1498 }
1499 #endif
1500
1501 #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B
1502 if (requested_freq_hz > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ)
1503 {
1504 /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as
1505 * a precondition to bsp_prv_clock_set. */
1506 BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES;
1507 }
1508 #endif
1509
1510 return new_rom_wait_state;
1511 }
1512
1513 /*******************************************************************************************************************//**
1514 * Decreases the ROM and RAM wait state settings to the minimum supported based on the applied clock change.
1515 *
1516 * @param[in] updated_freq_hz New clock frequency after clock change
1517 * @param[in] new_rom_wait_state Optimal value for FLWT if it exists, 0 if FLWT does not exist on the MCU
1518 **********************************************************************************************************************/
bsp_clock_set_postchange(uint32_t updated_freq_hz,uint8_t new_rom_wait_state)1519 static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_wait_state)
1520 {
1521 /* These variables are unused for some MCUs. */
1522 FSP_PARAMETER_NOT_USED(new_rom_wait_state);
1523 FSP_PARAMETER_NOT_USED(updated_freq_hz);
1524
1525 #if BSP_FEATURE_CGC_HAS_SRAMWTSC
1526
1527 /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */
1528 if (updated_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS)
1529 {
1530 #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1
1531 R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK;
1532 R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE;
1533 R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK;
1534 #else
1535 R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
1536 R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE;
1537 R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
1538 #endif
1539 }
1540 #endif
1541
1542 #if BSP_FEATURE_CGC_HAS_FLWT
1543 if (new_rom_wait_state != R_FCACHE->FLWT)
1544 {
1545 R_FCACHE->FLWT = new_rom_wait_state;
1546 }
1547 #endif
1548
1549 #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B
1550 if (updated_freq_hz <= BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ)
1551 {
1552 R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES;
1553 }
1554 #endif
1555
1556 #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B
1557 if (updated_freq_hz <= BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ)
1558 {
1559 BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES;
1560 }
1561 #endif
1562 }
1563
1564 /*******************************************************************************************************************//**
1565 * Octa-SPI clock update.
1566 * @param[in] p_octaclk_setting Pointer to Octaclk setting structure which provides information regarding
1567 * Octaclk source and divider settings to be applied.
1568 * @note The requested Octaclk source must be started before calling this function.
1569 **********************************************************************************************************************/
R_BSP_OctaclkUpdate(bsp_octaclk_settings_t * p_octaclk_setting)1570 void R_BSP_OctaclkUpdate (bsp_octaclk_settings_t * p_octaclk_setting)
1571 {
1572 #if BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK
1573
1574 /* Store initial value of CGC and LPM protection registers. */
1575 uint16_t bsp_prv_prcr_orig = R_SYSTEM->PRCR;
1576
1577 /* Unlock CGC and LPM protection registers. */
1578 R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK;
1579
1580 /* Request to change the OCTASPI Clock. */
1581 R_SYSTEM->OCTACKCR_b.OCTACKSREQ = 1;
1582
1583 /* Wait for the clock to be stopped. */
1584 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 1U);
1585
1586 /* Write the settings. */
1587 R_SYSTEM->OCTACKDIVCR = (uint8_t) p_octaclk_setting->divider;
1588 R_SYSTEM->OCTACKCR = (uint8_t) (p_octaclk_setting->source_clock | R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk);
1589
1590 /* Start the OCTASPI Clock by setting OCTACKSREQ to zero. */
1591 R_SYSTEM->OCTACKCR = (uint8_t) p_octaclk_setting->source_clock;
1592
1593 /* Wait for the OCTASPI Clock to be started. */
1594 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 0U);
1595
1596 /* Restore CGC and LPM protection registers. */
1597 R_SYSTEM->PRCR = bsp_prv_prcr_orig;
1598 #else
1599 FSP_PARAMETER_NOT_USED(p_octaclk_setting);
1600 #endif
1601 }
1602
1603 /*******************************************************************************************************************//**
1604 * Gets the frequency of a source clock.
1605 * @param[in] clock Pointer to Octaclk setting structure which provides information regarding
1606 * Octaclk source and divider settings to be applied.
1607 * @return Frequency of requested clock in Hertz.
1608 **********************************************************************************************************************/
R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock)1609 uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock)
1610 {
1611 uint32_t source_clock = g_clock_freq[clock];
1612
1613 return source_clock;
1614 }
1615
1616 /** @} (end addtogroup BSP_MCU_PRV) */
1617