1 #ifndef __BASE_ADDRESSES_H 2 #define __BASE_ADDRESSES_H 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 #if 33U == __CORTEX_M // NOLINT(readability-magic-numbers) 9 10 /* =========================================================================================================================== */ 11 /* ================ Device Specific Peripheral Address Map ================ */ 12 /* =========================================================================================================================== */ 13 14 /** @addtogroup Device_Peripheral_peripheralAddr 15 * @{ 16 */ 17 18 #define R_ACMPHS0_BASE 0x400F4000 19 #define R_ACMPHS1_BASE 0x400F4100 20 #define R_ACMPHS2_BASE 0x400F4200 21 #define R_ACMPHS3_BASE 0x400F4300 22 #define R_MPU_BASE 0x40000000 23 #define R_TZF_BASE 0x40000E00 24 #define R_SRAM_BASE 0x40002000 25 #define R_BUS_BASE 0x40003000 26 #define R_DMAC0_BASE 0x40005000 27 #define R_DMAC1_BASE 0x40005040 28 #define R_DMAC2_BASE 0x40005080 29 #define R_DMAC3_BASE 0x400050C0 30 #define R_DMAC4_BASE 0x40005100 31 #define R_DMAC5_BASE 0x40005140 32 #define R_DMAC6_BASE 0x40005180 33 #define R_DMAC7_BASE 0x400051C0 34 #define R_DMA_BASE 0x40005200 35 #define R_DTC_BASE 0x40005400 36 #define R_ICU_BASE 0x40006000 37 #define R_CACHE_BASE 0x40007000 38 #define R_CPSCU_BASE 0x40008000 39 #define R_DBG_BASE 0x4001B000 40 #define R_FCACHE_BASE 0x4001C000 41 #define R_SYSC_BASE 0x4001E000 42 #define R_IIRFA_BASE 0x40020000 43 #define R_TSN_CAL_BASE 0x407FB17C 44 #define R_TSN_CTRL_BASE 0x400F3000 45 #define R_ELC_BASE 0x40082000 46 #define R_TC_BASE 0x40083000 47 #define R_IWDT_BASE 0x40083200 48 #define R_WDT_BASE 0x40083400 49 #define R_CAC_BASE 0x40083600 50 #define R_MSTP_BASE 0x40084000 51 #define R_KINT_BASE 0x40085000 52 #define R_POEG_BASE 0x4008A000 53 #define R_USB_FS0_BASE 0x40090000 54 #define R_USB_HS0_BASE 0x40111000 55 #define R_SDHI0_BASE 0x40092000 56 #define R_SSI0_BASE 0x4009D000 57 #define R_IIC0_BASE 0x4009F000 58 #define R_IIC1_BASE 0x4009F100 59 #define R_OSPI_BASE 0x400A6000 60 #define R_CAN0_BASE 0x400A8000 61 #define R_CAN1_BASE 0x400A9000 62 #define R_CEC_BASE 0x400AC000 63 #define R_CANFD_BASE 0x400B0000 64 #define R_CTSU_BASE 0x400D0000 65 #define R_PSCU_BASE 0x400E0000 66 #define R_AGT0_BASE 0x400E8000 67 #define R_AGT1_BASE 0x400E8100 68 #define R_AGT2_BASE 0x400E8200 69 #define R_AGT3_BASE 0x400E8300 70 #define R_AGT4_BASE 0x400E8400 71 #define R_AGT5_BASE 0x400E8500 72 #define R_AGTW0_BASE 0x400E8000 73 #define R_AGTW1_BASE 0x400E8100 74 #define R_TSN_CTRL_BASE 0x400F3000 75 #define R_CRC_BASE 0x40108000 76 #define R_DOC_BASE 0x40109000 77 #define R_ETHERC_EDMAC_BASE 0x40114000 78 #define R_ETHERC0_BASE 0x40114100 79 #define R_SCI0_BASE 0x40118000 80 #define R_SCI1_BASE 0x40118100 81 #define R_SCI2_BASE 0x40118200 82 #define R_SCI3_BASE 0x40118300 83 #define R_SCI4_BASE 0x40118400 84 #define R_SCI5_BASE 0x40118500 85 #define R_SCI6_BASE 0x40118600 86 #define R_SCI7_BASE 0x40118700 87 #define R_SCI8_BASE 0x40118800 88 #define R_SCI9_BASE 0x40118900 89 #define R_SPI0_BASE 0x4011A000 90 #define R_SPI1_BASE 0x4011A100 91 #define R_SPI_B0_BASE 0x4011A000 92 #define R_SPI_B1_BASE 0x4011A100 93 #define R_GPT320_BASE 0x40169000 94 #define R_GPT321_BASE 0x40169100 95 #define R_GPT322_BASE 0x40169200 96 #define R_GPT323_BASE 0x40169300 97 #define R_GPT164_BASE 0x40169400 98 #define R_GPT165_BASE 0x40169500 99 #define R_GPT166_BASE 0x40169600 100 #define R_GPT167_BASE 0x40169700 101 #define R_GPT168_BASE 0x40169800 102 #define R_GPT169_BASE 0x40169900 103 #define R_GPT_OPS_BASE 0x40169A00 104 #define R_GPT_ODC_BASE 0x4016A000 105 #define R_GPT_GTCLK_BASE 0x40169B00 106 #define R_ADC120_BASE 0x40170000 107 #define R_ADC121_BASE 0x40170200 108 109 /* Not included in SVD */ 110 #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) 111 #define R_DAC120_BASE 0x40172000 112 #define R_DAC121_BASE 0x40172100 113 #else 114 #define R_DAC12_BASE 0x40171000 115 #endif 116 #define R_FLAD_BASE 0x407FC000 117 #define R_FACI_HP_CMD_BASE 0x407E0000 118 #define R_FACI_HP_BASE 0x407FE000 119 #define R_QSPI_BASE 0x64000000 120 #define R_TFU_BASE 0x40021000 121 122 /* Not included in SVD */ 123 #if (2U == BSP_FEATURE_IOPORT_VERSION) 124 #define R_PORT0_BASE 0x4001F000 125 #define R_PORT1_BASE 0x4001F020 126 #define R_PORT2_BASE 0x4001F040 127 #define R_PORT10_BASE 0x4001F140 128 #define R_PORT11_BASE 0x4001F160 129 #define R_PORT12_BASE 0x4001F180 130 #define R_PORT13_BASE 0x4001F1A0 131 #define R_PORT14_BASE 0x4001F1C0 132 #define R_PFS_BASE 0x4001F800 133 #define R_PMISC_BASE 0x4001FD00 134 #else 135 #define R_PORT0_BASE 0x40080000 136 #define R_PORT1_BASE 0x40080020 137 #define R_PORT2_BASE 0x40080040 138 #define R_PORT3_BASE 0x40080060 139 #define R_PORT4_BASE 0x40080080 140 #define R_PORT5_BASE 0x400800A0 141 #define R_PORT6_BASE 0x400800C0 142 #define R_PORT7_BASE 0x400800E0 143 #define R_PORT8_BASE 0x40080100 144 #define R_PORT9_BASE 0x40080120 145 #define R_PORT10_BASE 0x40080140 146 #define R_PORT11_BASE 0x40080160 147 #define R_PFS_BASE 0x40080800 148 #define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this 149 #endif 150 #define R_GPT_POEG0_BASE 0x4008A000 151 #define R_GPT_POEG1_BASE 0x4008A100 152 #define R_GPT_POEG2_BASE 0x4008A200 153 #define R_GPT_POEG3_BASE 0x4008A300 154 155 #define R_RTC_BASE 0x40083000 156 157 #define R_I3C0_BASE 0x4011F000 158 #define R_I3C1_BASE 0x4011F400 159 160 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 161 162 /* =========================================================================================================================== */ 163 /* ================ Peripheral declaration ================ */ 164 /* =========================================================================================================================== */ 165 166 /** @addtogroup Device_Peripheral_declaration 167 * @{ 168 */ 169 170 // #define R_MPU ((R_MPU_Type *) R_MPU_BASE) 171 #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) 172 #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) 173 #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) 174 #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) 175 #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) 176 #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) 177 #define R_TZF ((R_TZF_Type *) R_TZF_BASE) 178 #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) 179 #define R_BUS ((R_BUS_B_Type *) R_BUS_BASE) 180 #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) 181 #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) 182 #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) 183 #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) 184 #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) 185 #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) 186 #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) 187 #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) 188 #define R_DMA ((R_DMA_Type *) R_DMA_BASE) 189 #define R_DTC ((R_DTC_Type *) R_DTC_BASE) 190 #define R_ICU ((R_ICU_Type *) R_ICU_BASE) 191 #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) 192 #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) 193 #define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE) 194 #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) 195 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE) 196 #define R_IIRFA ((R_IIRFA_Type *) R_IIRFA_BASE) 197 #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) 198 #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) 199 #define R_PFS ((R_PFS_Type *) R_PFS_BASE) 200 #define R_ELC ((R_ELC_Type *) R_ELC_BASE) 201 #define R_TC ((R_TC_Type *) R_TC_BASE) 202 #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) 203 #define R_KINT ((R_KINT_Type *) R_KINT_BASE) 204 #define R_WDT ((R_WDT_Type *) R_WDT_BASE) 205 #define R_CAC ((R_CAC_Type *) R_CAC_BASE) 206 #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) 207 #define R_POEG ((R_POEG_Type *) R_POEG_BASE) 208 #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) 209 #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) 210 #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) 211 #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) 212 #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) 213 #define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE) 214 #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) 215 #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) 216 #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) 217 #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) 218 #define R_CEC ((R_CEC_Type *) R_CEC_BASE) 219 #if BSP_FEATURE_CANFD_LITE 220 #define R_CANFD ((R_CANFDL_Type *) R_CANFD_BASE) 221 #else 222 #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) 223 #endif 224 #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) 225 #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) 226 #if BSP_FEATURE_AGT_HAS_AGTW 227 #define R_AGT0 ((R_AGTW0_Type *) R_AGT0_BASE) 228 #define R_AGT1 ((R_AGTW0_Type *) R_AGT1_BASE) 229 #define R_AGT2 ((R_AGTW0_Type *) R_AGT2_BASE) 230 #define R_AGT3 ((R_AGTW0_Type *) R_AGT3_BASE) 231 #define R_AGT4 ((R_AGTW0_Type *) R_AGT4_BASE) 232 #define R_AGT5 ((R_AGTW0_Type *) R_AGT5_BASE) 233 #else 234 #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) 235 #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) 236 #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) 237 #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) 238 #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) 239 #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) 240 #endif 241 #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE) 242 #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE) 243 #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) 244 #define R_CRC ((R_CRC_Type *) R_CRC_BASE) 245 #if (2U == BSP_FEATURE_DOC_VERSION) 246 #define R_DOC_B ((R_DOC_B_Type *) R_DOC_BASE) 247 #else 248 #define R_DOC ((R_DOC_Type *) R_DOC_BASE) 249 #endif 250 #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) 251 #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) 252 #if (2U == BSP_FEATURE_SCI_VERSION) 253 #define R_SCI0 ((R_SCI_B0_Type *) R_SCI0_BASE) 254 #define R_SCI1 ((R_SCI_B0_Type *) R_SCI1_BASE) 255 #define R_SCI2 ((R_SCI_B0_Type *) R_SCI2_BASE) 256 #define R_SCI3 ((R_SCI_B0_Type *) R_SCI3_BASE) 257 #define R_SCI4 ((R_SCI_B0_Type *) R_SCI4_BASE) 258 #define R_SCI9 ((R_SCI_B0_Type *) R_SCI9_BASE) 259 #else 260 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) 261 #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) 262 #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) 263 #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) 264 #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) 265 #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) 266 #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) 267 #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) 268 #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) 269 #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) 270 #endif 271 #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) 272 #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) 273 #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) 274 #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) 275 #define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE) 276 #define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE) 277 #define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE) 278 #define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE) 279 #define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE) 280 #define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE) 281 #define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE) 282 #define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE) 283 #define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE) 284 #define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE) 285 #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) 286 #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) 287 #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE) 288 #define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE) 289 #define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE) 290 #define R_ADC_B ((R_ADC_B0_Type *) R_ADC120_BASE) 291 #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) 292 #define R_DAC0 ((R_DAC_Type *) R_DAC120_BASE) 293 #define R_DAC1 ((R_DAC_Type *) R_DAC121_BASE) 294 #else 295 #define R_DAC ((R_DAC_Type *) R_DAC12_BASE) 296 #endif 297 #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) 298 #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) 299 #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) 300 #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) 301 #define R_TFU ((R_TFU_Type *) R_TFU_BASE) 302 #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) 303 #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) 304 305 /* Not in SVD. */ 306 307 #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) 308 #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) 309 #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) 310 #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) 311 #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) 312 #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) 313 #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) 314 #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) 315 #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) 316 #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) 317 #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) 318 #if (2U == BSP_FEATURE_IOPORT_VERSION) 319 #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) 320 #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) 321 #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) 322 #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) 323 #endif 324 #define R_PFS ((R_PFS_Type *) R_PFS_BASE) 325 #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) 326 327 #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) 328 #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) 329 #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) 330 #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) 331 332 #define R_RTC ((R_RTC_Type *) R_RTC_BASE) 333 334 /** @} */ /* End of group Device_Peripheral_declaration */ 335 336 #else 337 338 /* =========================================================================================================================== */ 339 /* ================ Device Specific Peripheral Address Map ================ */ 340 /* =========================================================================================================================== */ 341 342 /** @addtogroup Device_Peripheral_peripheralAddr 343 * @{ 344 */ 345 346 #define R_ACMPHS0_BASE 0x40085000 347 #define R_ACMPHS1_BASE 0x40085100 348 #define R_ACMPHS2_BASE 0x40085200 349 #define R_ACMPHS3_BASE 0x40085300 350 #define R_ACMPHS4_BASE 0x40085400 351 #define R_ACMPHS5_BASE 0x40085500 352 #define R_ACMPLP_BASE 0x40085E00 353 #define R_ADC0_BASE 0x4005C000 354 #define R_ADC1_BASE 0x4005C200 355 #define R_AGT0_BASE 0x40084000 356 #define R_AGT1_BASE 0x40084100 357 #define R_AGTW0_BASE 0x40084000 358 #define R_AGTW1_BASE 0x40084100 359 #define R_BUS_BASE 0x40003000 360 #define R_CAC_BASE 0x40044600 361 #define R_CAN0_BASE 0x40050000 362 #define R_CAN1_BASE 0x40051000 363 #define R_CRC_BASE 0x40074000 364 #define R_CTSU_BASE 0x40081000 365 #define R_CTSU2_BASE 0x40082000 366 #define R_DAC_BASE 0x4005E000 367 #define R_DAC8_BASE 0x4009E000 368 #define R_DALI0_BASE 0x4008F000 369 #define R_DEBUG_BASE 0x4001B000 370 #define R_DMA_BASE 0x40005200 371 #define R_DMAC0_BASE 0x40005000 372 #define R_DMAC1_BASE 0x40005040 373 #define R_DMAC2_BASE 0x40005080 374 #define R_DMAC3_BASE 0x400050C0 375 #define R_DMAC4_BASE 0x40005100 376 #define R_DMAC5_BASE 0x40005140 377 #define R_DMAC6_BASE 0x40005180 378 #define R_DMAC7_BASE 0x400051C0 379 #define R_DOC_BASE 0x40054100 380 #define R_DRW_BASE 0x400E4000 381 #define R_DTC_BASE 0x40005400 382 #define R_ELC_BASE 0x40041000 383 #define R_ETHERC0_BASE 0x40064100 384 #define R_ETHERC_EDMAC_BASE 0x40064000 385 #define R_PTP_EDMAC_BASE 0x40064400 386 #define R_ETHERC_EPTPC_BASE 0x40065800 387 #define R_ETHERC_EPTPC1_BASE 0x40065C00 388 #define R_ETHERC_EPTPC_CFG_BASE 0x40064500 389 #define R_ETHERC_EPTPC_COMMON_BASE 0x40065000 390 #define R_FACI_HP_CMD_BASE 0x407E0000 391 #define R_FACI_HP_BASE 0x407FE000 392 #define R_FACI_LP_BASE 0x407EC000 393 #define R_CTSUTRIM_BASE 0x407EC000 394 #define R_FCACHE_BASE 0x4001C000 395 #define R_GLCDC_BASE 0x400E0000 396 #define R_GPT0_BASE 0x40078000 397 #define R_GPT1_BASE 0x40078100 398 #define R_GPT2_BASE 0x40078200 399 #define R_GPT3_BASE 0x40078300 400 #define R_GPT4_BASE 0x40078400 401 #define R_GPT5_BASE 0x40078500 402 #define R_GPT6_BASE 0x40078600 403 #define R_GPT7_BASE 0x40078700 404 #define R_GPT8_BASE 0x40078800 405 #define R_GPT9_BASE 0x40078900 406 #define R_GPT10_BASE 0x40078A00 407 #define R_GPT11_BASE 0x40078B00 408 #define R_GPT12_BASE 0x40078C00 409 #define R_GPT13_BASE 0x40078D00 410 #define R_GPT_ODC_BASE 0x4007B000 411 #define R_GPT_OPS_BASE 0x40078FF0 412 #define R_GPT_POEG0_BASE 0x40042000 413 #define R_GPT_POEG1_BASE 0x40042100 414 #define R_GPT_POEG2_BASE 0x40042200 415 #define R_GPT_POEG3_BASE 0x40042300 416 #define R_I3C0_BASE 0x40083000 417 #define R_ICU_BASE 0x40006000 418 #define R_IIC0_BASE 0x40053000 419 #define R_IIC1_BASE 0x40053100 420 #define R_IIC2_BASE 0x40053200 421 #define R_IRDA_BASE 0x40070F00 422 #define R_IWDT_BASE 0x40044400 423 #define R_JPEG_BASE 0x400E6000 424 #define R_KINT_BASE 0x40080000 425 #define R_MMF_BASE 0x40001000 426 #define R_MPU_MMPU_BASE 0x40000000 427 #define R_MPU_SMPU_BASE 0x40000C00 428 #define R_MPU_SPMON_BASE 0x40000D00 429 #define R_MSTP_BASE (0x40047000 - 4U) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ 430 #define R_OPAMP_BASE 0x40086000 431 #define R_OPAMP2_BASE 0x400867F8 432 #define R_PDC_BASE 0x40094000 433 #define R_PORT0_BASE 0x40040000 434 #define R_PORT1_BASE 0x40040020 435 #define R_PORT2_BASE 0x40040040 436 #define R_PORT3_BASE 0x40040060 437 #define R_PORT4_BASE 0x40040080 438 #define R_PORT5_BASE 0x400400A0 439 #define R_PORT6_BASE 0x400400C0 440 #define R_PORT7_BASE 0x400400E0 441 #define R_PORT8_BASE 0x40040100 442 #define R_PORT9_BASE 0x40040120 443 #define R_PORT10_BASE 0x40040140 444 #define R_PORT11_BASE 0x40040160 445 #define R_PFS_BASE 0x40040800 446 #define R_PMISC_BASE 0x40040D00 447 #define R_QSPI_BASE 0x64000000 448 #define R_RTC_BASE 0x40044000 449 #define R_SCI0_BASE 0x40070000 450 #define R_SCI1_BASE 0x40070020 451 #define R_SCI2_BASE 0x40070040 452 #define R_SCI3_BASE 0x40070060 453 #define R_SCI4_BASE 0x40070080 454 #define R_SCI5_BASE 0x400700A0 455 #define R_SCI6_BASE 0x400700C0 456 #define R_SCI7_BASE 0x400700E0 457 #define R_SCI8_BASE 0x40070100 458 #define R_SCI9_BASE 0x40070120 459 #define R_SDADC0_BASE 0x4009C000 460 #define R_SDHI0_BASE 0x40062000 461 #define R_SDHI1_BASE 0x40062400 462 #define R_SLCDC_BASE 0x40082000 463 #define R_SPI0_BASE 0x40072000 464 #define R_SPI1_BASE 0x40072100 465 #define R_SRAM_BASE 0x40002000 466 #define R_SRC_BASE 0x40048000 467 #define R_SSI0_BASE 0x4004E000 468 #define R_SSI1_BASE 0x4004E100 469 #define R_SYSTEM_BASE 0x4001E000 470 #define R_TSN_BASE 0x407EC000 471 #define R_TSN_CAL_BASE 0x407FB17C 472 #define R_TSN_CTRL_BASE 0x4005D000 473 #define R_USB_FS0_BASE 0x40090000 474 #define R_USB_HS0_BASE 0x40060000 475 #define R_WDT_BASE 0x40044200 476 477 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 478 479 /* =========================================================================================================================== */ 480 /* ================ Peripheral declaration ================ */ 481 /* =========================================================================================================================== */ 482 483 /** @addtogroup Device_Peripheral_declaration 484 * @{ 485 */ 486 487 #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) 488 #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) 489 #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) 490 #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) 491 #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) 492 #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) 493 #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) 494 #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) 495 #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) 496 #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) 497 #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) 498 #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE) 499 #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE) 500 #define R_BUS ((R_BUS_Type *) R_BUS_BASE) 501 #define R_CAC ((R_CAC_Type *) R_CAC_BASE) 502 #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) 503 #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) 504 #define R_CRC ((R_CRC_Type *) R_CRC_BASE) 505 #if (2U == BSP_FEATURE_CTSU_VERSION) 506 #define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE) 507 #else 508 #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) 509 #endif 510 #define R_DAC ((R_DAC_Type *) R_DAC_BASE) 511 #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE) 512 #define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE) 513 #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) 514 #define R_DMA ((R_DMA_Type *) R_DMA_BASE) 515 #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) 516 #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) 517 #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) 518 #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) 519 #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) 520 #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) 521 #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) 522 #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) 523 #define R_DOC ((R_DOC_Type *) R_DOC_BASE) 524 #define R_DRW ((R_DRW_Type *) R_DRW_BASE) 525 #define R_DTC ((R_DTC_Type *) R_DTC_BASE) 526 #define R_ELC ((R_ELC_Type *) R_ELC_BASE) 527 #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) 528 #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) 529 #define R_PTP_EDMAC ((R_ETHERC_EDMAC_Type *) R_PTP_EDMAC_BASE) 530 #define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE) 531 #define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC0_Type *) R_ETHERC_EPTPC1_BASE) 532 #define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE) 533 #define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE) 534 #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) 535 #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) 536 #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) 537 #define R_CTSUTRIM ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE) 538 #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) 539 #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) 540 #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) 541 #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) 542 #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) 543 #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) 544 #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) 545 #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) 546 #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) 547 #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) 548 #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) 549 #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) 550 #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) 551 #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) 552 #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) 553 #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) 554 #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) 555 #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) 556 #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) 557 #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) 558 #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) 559 #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) 560 #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) 561 #define R_ICU ((R_ICU_Type *) R_ICU_BASE) 562 #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) 563 #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) 564 #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) 565 #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) 566 #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) 567 #define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE) 568 #define R_KINT ((R_KINT_Type *) R_KINT_BASE) 569 #define R_MMF ((R_MMF_Type *) R_MMF_BASE) 570 #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) 571 #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) 572 #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) 573 #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) 574 #if (2U == BSP_FEATURE_OPAMP_BASE_ADDRESS) 575 #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE) 576 #else 577 #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE) 578 #endif 579 #define R_PDC ((R_PDC_Type *) R_PDC_BASE) 580 #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) 581 #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) 582 #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) 583 #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) 584 #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) 585 #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) 586 #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) 587 #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) 588 #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) 589 #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) 590 #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) 591 #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) 592 #define R_PFS ((R_PFS_Type *) R_PFS_BASE) 593 #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) 594 #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) 595 #define R_RTC ((R_RTC_Type *) R_RTC_BASE) 596 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) 597 #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) 598 #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) 599 #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) 600 #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) 601 #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) 602 #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) 603 #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) 604 #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) 605 #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) 606 #define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE) 607 #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) 608 #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) 609 #define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE) 610 #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) 611 #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) 612 #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) 613 #define R_SRC ((R_SRC_Type *) R_SRC_BASE) 614 #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) 615 #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) 616 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) 617 #define R_TSN ((R_TSN_Type *) R_TSN_BASE) 618 #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) 619 #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) 620 #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) 621 #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) 622 #define R_WDT ((R_WDT_Type *) R_WDT_BASE) 623 624 /** @} */ /* End of group Device_Peripheral_declaration */ 625 626 #endif 627 628 #ifdef __cplusplus 629 } 630 #endif 631 632 #endif 633