1 /*********************************************************************************************************************** 2 * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 /*******************************************************************************************************************//** 22 * @ingroup RENESAS_INTERFACES 23 * @defgroup IOPORT_API I/O Port Interface 24 * @brief Interface for accessing I/O ports and configuring I/O functionality. 25 * 26 * @section IOPORT_API_SUMMARY Summary 27 * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. 28 * Port and pin direction can be changed. 29 * 30 * IOPORT Interface description: @ref IOPORT 31 * 32 * @{ 33 **********************************************************************************************************************/ 34 35 #ifndef R_IOPORT_API_H 36 #define R_IOPORT_API_H 37 38 /*********************************************************************************************************************** 39 * Includes 40 **********************************************************************************************************************/ 41 42 /* Common error codes and definitions. */ 43 #include "bsp_api.h" 44 45 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 46 FSP_HEADER 47 48 /********************************************************************************************************************** 49 * Macro definitions 50 **********************************************************************************************************************/ 51 52 /* Private definition to set enumeration values. */ 53 #define IOPORT_PRV_PFS_PSEL_OFFSET (24) 54 55 /********************************************************************************************************************** 56 * Typedef definitions 57 **********************************************************************************************************************/ 58 59 /** IO port type used with ports */ 60 typedef uint16_t ioport_size_t; ///< IO port size on this device 61 62 /** Superset of all peripheral functions. */ 63 typedef enum e_ioport_peripheral 64 { 65 /** Pin will functions as an IO pin */ 66 IOPORT_PERIPHERAL_IO = 0x00, 67 68 /** Pin will function as a DEBUG pin */ 69 IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), 70 71 /** Pin will function as an AGT peripheral pin */ 72 IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), 73 74 /** Pin will function as a GPT peripheral pin */ 75 IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), 76 77 /** Pin will function as a GPT peripheral pin */ 78 IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), 79 80 /** Pin will function as an SCI peripheral pin */ 81 IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), 82 83 /** Pin will function as an SCI peripheral pin */ 84 IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), 85 86 /** Pin will function as a SPI peripheral pin */ 87 IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), 88 89 /** Pin will function as a IIC peripheral pin */ 90 IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), 91 92 /** Pin will function as a KEY peripheral pin */ 93 IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), 94 95 /** Pin will function as a clock/comparator/RTC peripheral pin */ 96 IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), 97 98 /** Pin will function as a CAC/ADC peripheral pin */ 99 IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), 100 101 /** Pin will function as a BUS peripheral pin */ 102 IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), 103 104 /** Pin will function as a CTSU peripheral pin */ 105 IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), 106 107 /** Pin will function as a CMPHS peripheral pin */ 108 IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), 109 110 /** Pin will function as a segment LCD peripheral pin */ 111 IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 112 113 /** Pin will function as an SCI peripheral DEn pin */ 114 IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 115 116 /** Pin will function as a DALI peripheral pin */ 117 IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), 118 119 /** Pin will function as an SCI DEn peripheral pin */ 120 IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), 121 122 /** Pin will function as a CAN peripheral pin */ 123 IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), 124 125 /** Pin will function as a QSPI peripheral pin */ 126 IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), 127 128 /** Pin will function as an SSI peripheral pin */ 129 IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), 130 131 /** Pin will function as a USB full speed peripheral pin */ 132 IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), 133 134 /** Pin will function as a USB high speed peripheral pin */ 135 IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), 136 137 /** Pin will function as a GPT peripheral pin */ 138 IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), 139 140 /** Pin will function as an SD/MMC peripheral pin */ 141 IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), 142 143 /** Pin will function as a GPT peripheral pin */ 144 IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), 145 146 /** Pin will function as an Ethernet MMI peripheral pin */ 147 IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), 148 149 /** Pin will function as a GPT peripheral pin */ 150 IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), 151 152 /** Pin will function as an Ethernet RMMI peripheral pin */ 153 IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), 154 155 /** Pin will function as a PDC peripheral pin */ 156 IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), 157 158 /** Pin will function as a graphics LCD peripheral pin */ 159 IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), 160 161 /** Pin will function as a CAC peripheral pin */ 162 IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), 163 164 /** Pin will function as a debug trace peripheral pin */ 165 IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), 166 167 /** Pin will function as a OSPI peripheral pin */ 168 IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), 169 170 /** Pin will function as a CEC peripheral pin */ 171 IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 172 173 /** Pin will function as a PGAOUT peripheral pin */ 174 IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 175 176 /** Pin will function as a PGAOUT peripheral pin */ 177 IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), 178 } ioport_peripheral_t; 179 180 /* DEPRECATED Superset of Ethernet channels. */ 181 typedef enum e_ioport_eth_ch 182 { 183 IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0 184 IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1 185 IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking 186 } ioport_ethernet_channel_t; 187 188 /* DEPRECATED Superset of Ethernet PHY modes. */ 189 typedef enum e_ioport_eth_mode 190 { 191 IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII 192 IOPORT_ETHERNET_MODE_MII = 0x10, ///< Ethernet PHY mode set to RMII 193 IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking 194 } ioport_ethernet_mode_t; 195 196 /** Options to configure pin functions */ 197 typedef enum e_ioport_cfg_options 198 { 199 IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) 200 IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output 201 IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low 202 IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high 203 IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up 204 IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode 205 IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output 206 IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput 207 IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium 208 IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed 209 IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port 210 IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high 211 IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge 212 IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge 213 IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges 214 IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin 215 IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin 216 IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin 217 } ioport_cfg_options_t; 218 219 /* PFS writing enable/disable. */ 220 typedef enum e_ioport_pwpr 221 { 222 IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access 223 IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access 224 } ioport_pwpr_t; 225 226 /** Pin identifier and pin PFS pin configuration value */ 227 typedef struct st_ioport_pin_cfg 228 { 229 uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure 230 bsp_io_port_pin_t pin; ///< Pin identifier 231 } ioport_pin_cfg_t; 232 233 /** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */ 234 typedef struct st_ioport_cfg 235 { 236 uint16_t number_of_pins; ///< Number of pins for which there is configuration data 237 ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data 238 } ioport_cfg_t; 239 240 /** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. 241 * @par Implemented as 242 * - ioport_instance_ctrl_t 243 */ 244 typedef void ioport_ctrl_t; 245 246 /** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ 247 typedef struct st_ioport_api 248 { 249 /** Initialize internal driver data and initial pin configurations. Called during startup. Do 250 * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of 251 * multiple pins. 252 * @par Implemented as 253 * - @ref R_IOPORT_Open() 254 * @param[in] p_cfg Pointer to pin configuration data array. 255 */ 256 fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); 257 258 /** Close the API. 259 * @par Implemented as 260 * - @ref R_IOPORT_Close() 261 * 262 * @param[in] p_ctrl Pointer to control structure. 263 **/ 264 fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); 265 266 /** Configure multiple pins. 267 * @par Implemented as 268 * - @ref R_IOPORT_PinsCfg() 269 * @param[in] p_cfg Pointer to pin configuration data array. 270 */ 271 fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); 272 273 /** Configure settings for an individual pin. 274 * @par Implemented as 275 * - @ref R_IOPORT_PinCfg() 276 * @param[in] pin Pin to be read. 277 * @param[in] cfg Configuration options for the pin. 278 */ 279 fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); 280 281 /** Read the event input data of the specified pin and return the level. 282 * @par Implemented as 283 * - @ref R_IOPORT_PinEventInputRead() 284 * @param[in] pin Pin to be read. 285 * @param[in] p_pin_event Pointer to return the event data. 286 */ 287 fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); 288 289 /** Write pin event data. 290 * @par Implemented as 291 * - @ref R_IOPORT_PinEventOutputWrite() 292 * @param[in] pin Pin event data is to be written to. 293 * @param[in] pin_value Level to be written to pin output event. 294 */ 295 fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); 296 297 /* DEPRECATED Configure the PHY mode of the Ethernet channels. 298 * @par Implemented as 299 * - @ref R_IOPORT_EthernetModeCfg() 300 * @param[in] channel Channel configuration will be set for. 301 * @param[in] mode PHY mode to set the channel to. 302 */ 303 fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel, 304 ioport_ethernet_mode_t mode); 305 306 /** Read level of a pin. 307 * @par Implemented as 308 * - @ref R_IOPORT_PinRead() 309 * @param[in] pin Pin to be read. 310 * @param[in] p_pin_value Pointer to return the pin level. 311 */ 312 fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); 313 314 /** Write specified level to a pin. 315 * @par Implemented as 316 * - @ref R_IOPORT_PinWrite() 317 * @param[in] pin Pin to be written to. 318 * @param[in] level State to be written to the pin. 319 */ 320 fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); 321 322 /** Set the direction of one or more pins on a port. 323 * @par Implemented as 324 * - @ref R_IOPORT_PortDirectionSet() 325 * @param[in] port Port being configured. 326 * @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input). 327 * @param[in] mask Mask controlling which pins on the port are to be configured. 328 */ 329 fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, 330 ioport_size_t mask); 331 332 /** Read captured event data for a port. 333 * @par Implemented as 334 * - @ref R_IOPORT_PortEventInputRead() 335 * @param[in] port Port to be read. 336 * @param[in] p_event_data Pointer to return the event data. 337 */ 338 fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); 339 340 /** Write event output data for a port. 341 * @par Implemented as 342 * - @ref R_IOPORT_PortEventOutputWrite() 343 * @param[in] port Port event data will be written to. 344 * @param[in] event_data Data to be written as event data to specified port. 345 * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. 346 * being written to port. 347 */ 348 fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, 349 ioport_size_t mask_value); 350 351 /** Read states of pins on the specified port. 352 * @par Implemented as 353 * - @ref R_IOPORT_PortRead() 354 * @param[in] port Port to be read. 355 * @param[in] p_port_value Pointer to return the port value. 356 */ 357 fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); 358 359 /** Write to multiple pins on a port. 360 * @par Implemented as 361 * - @ref R_IOPORT_PortWrite() 362 * @param[in] port Port to be written to. 363 * @param[in] value Value to be written to the port. 364 * @param[in] mask Mask controlling which pins on the port are written to. 365 */ 366 fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); 367 } ioport_api_t; 368 369 /** This structure encompasses everything that is needed to use an instance of this interface. */ 370 typedef struct st_ioport_instance 371 { 372 ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance 373 ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance 374 ioport_api_t const * p_api; ///< Pointer to the API structure for this instance 375 } ioport_instance_t; 376 377 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 378 FSP_FOOTER 379 380 #endif 381 382 /*******************************************************************************************************************//** 383 * @} (end defgroup IOPORT_API) 384 **********************************************************************************************************************/ 385