xref: /aosp_15_r20/external/coreboot/src/soc/amd/common/block/psp/psp_gen2.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <timer.h>
4 #include <types.h>
5 #include <amdblocks/psp.h>
6 #include <amdblocks/smn.h>
7 #include "psp_def.h"
8 
9 #define PSP_MAILBOX_COMMAND_OFFSET	0x10570 /* 4 bytes */
10 #define PSP_MAILBOX_BUFFER_L_OFFSET	0x10574 /* 4 bytes */
11 #define PSP_MAILBOX_BUFFER_H_OFFSET	0x10578 /* 4 bytes */
12 
13 union pspv2_mbox_command {
14 	u32 val;
15 	struct pspv2_mbox_cmd_fields {
16 		u16 mbox_status;
17 		u8 mbox_command;
18 		u32 reserved:6;
19 		u32 recovery:1;
20 		u32 ready:1;
21 	} __packed fields;
22 };
23 
rd_mbox_sts(void)24 static u16 rd_mbox_sts(void)
25 {
26 	union pspv2_mbox_command tmp;
27 
28 	tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET);
29 	return tmp.fields.mbox_status;
30 }
31 
wr_mbox_cmd(u8 cmd)32 static void wr_mbox_cmd(u8 cmd)
33 {
34 	union pspv2_mbox_command tmp = { .val = 0 };
35 
36 	/* Write entire 32-bit area to begin command execution */
37 	tmp.fields.mbox_command = cmd;
38 	smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET, tmp.val);
39 }
40 
rd_mbox_recovery(void)41 static u8 rd_mbox_recovery(void)
42 {
43 	union pspv2_mbox_command tmp;
44 
45 	tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET);
46 	return !!tmp.fields.recovery;
47 }
48 
wr_mbox_buffer_ptr(void * buffer)49 static void wr_mbox_buffer_ptr(void *buffer)
50 {
51 	const uint32_t buf_addr_h = (uint64_t)(uintptr_t)buffer >> 32;
52 	const uint32_t buf_addr_l = (uint64_t)(uintptr_t)buffer & 0xffffffff;
53 	smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_H_OFFSET, buf_addr_h);
54 	smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_L_OFFSET, buf_addr_l);
55 }
56 
wait_command(bool wait_for_ready)57 static int wait_command(bool wait_for_ready)
58 {
59 	union pspv2_mbox_command and_mask = { .val = ~0 };
60 	union pspv2_mbox_command expected = { .val = 0 };
61 	struct stopwatch sw;
62 	u32 tmp;
63 
64 	/* Zero fields from and_mask that should be kept */
65 	and_mask.fields.mbox_command = 0;
66 	and_mask.fields.ready = wait_for_ready ? 0 : 1;
67 
68 	/* Expect mbox_cmd == 0 but ready depends */
69 	if (wait_for_ready)
70 		expected.fields.ready = 1;
71 
72 	stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT);
73 
74 	do {
75 		tmp = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET);
76 		tmp &= ~and_mask.val;
77 		if (tmp == expected.val)
78 			return 0;
79 	} while (!stopwatch_expired(&sw));
80 
81 	return -PSPSTS_CMD_TIMEOUT;
82 }
83 
send_psp_command(u32 command,void * buffer)84 int send_psp_command(u32 command, void *buffer)
85 {
86 	if (rd_mbox_recovery())
87 		return -PSPSTS_RECOVERY;
88 
89 	if (wait_command(true))
90 		return -PSPSTS_CMD_TIMEOUT;
91 
92 	/* set address of command-response buffer and write command register */
93 	wr_mbox_buffer_ptr(buffer);
94 	wr_mbox_cmd(command);
95 
96 	/* PSP clears command register when complete.  All commands except
97 	 * SxInfo set the Ready bit. */
98 	if (wait_command(command != MBOX_BIOS_CMD_SX_INFO))
99 		return -PSPSTS_CMD_TIMEOUT;
100 
101 	/* check delivery status */
102 	if (rd_mbox_sts())
103 		return -PSPSTS_SEND_ERROR;
104 
105 	return 0;
106 }
107 
soc_read_c2p38(void)108 uint32_t soc_read_c2p38(void)
109 {
110 	return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
111 }
112