1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 4 #ifndef AMD_COMMON_PSP_EFS_H 5 #define AMD_COMMON_PSP_EFS_H 6 7 #include <types.h> 8 9 #define EFS_OFFSET CONFIG_AMD_FWM_POSITION 10 11 #define EMBEDDED_FW_SIGNATURE 0x55aa55aa 12 13 #if CONFIG(SOC_AMD_STONEYRIDGE) 14 #define SPI_MODE_FIELD spi_readmode_f15_mod_60_6f 15 #define SPI_SPEED_FIELD fast_speed_new_f15_mod_60_6f 16 #elif CONFIG(SOC_AMD_PICASSO) 17 #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f 18 #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f 19 #elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_MENDOCINO) 20 #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f 21 #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f 22 #endif 23 24 struct second_gen_efs { /* todo: expand for Server products */ 25 uint32_t gen:1; /* Client products only use bit 0 */ 26 uint32_t reserved:31; 27 } __packed; 28 29 #define EFS_SECOND_GEN 0 30 31 /* Copied from coreboot/util/amdfwtool.h */ 32 struct embedded_firmware { 33 uint32_t signature; /* 0x55aa55aa */ 34 uint32_t imc_entry; 35 uint32_t gec_entry; 36 uint32_t xhci_entry; 37 uint32_t psp_directory; 38 uint32_t new_psp_directory; 39 uint32_t bios0_entry; 40 uint32_t bios1_entry; 41 uint32_t bios2_entry; 42 struct second_gen_efs efs_gen; 43 uint32_t bios3_entry; 44 uint32_t reserved_2Ch; 45 uint32_t promontory_fw_ptr; 46 uint32_t lp_promontory_fw_ptr; 47 uint32_t reserved_38h; 48 uint32_t reserved_3Ch; 49 uint8_t spi_readmode_f15_mod_60_6f; 50 uint8_t fast_speed_new_f15_mod_60_6f; 51 uint8_t reserved_42h; 52 uint8_t spi_readmode_f17_mod_00_2f; 53 uint8_t spi_fastspeed_f17_mod_00_2f; 54 uint8_t qpr_dummy_cycle_f17_mod_00_2f; 55 uint8_t reserved_46h; 56 uint8_t spi_readmode_f17_mod_30_3f; 57 uint8_t spi_fastspeed_f17_mod_30_3f; 58 uint8_t micron_detect_f17_mod_30_3f; 59 uint8_t reserved_4Ah; 60 uint8_t reserved_4Bh; 61 uint32_t reserved_4Ch; 62 } __packed __aligned(16); 63 64 bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed); 65 66 #endif /* AMD_COMMON_PSP_EFS_H */ 67