1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <inttypes.h>
9 #include <stdint.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <drivers/arm/gicv2.h>
14 #include <lib/mmio.h>
15 #include <lib/xlat_tables/xlat_mmu_helpers.h>
16 #include <lib/xlat_tables/xlat_tables_defs.h>
17 #include <lib/xlat_tables/xlat_tables_v2.h>
18 #include <plat/common/platform.h>
19 #include <platform_def.h>
20
21 #include <rpi_shared.h>
22
23 /*
24 * Fields at the beginning of armstub8.bin.
25 * While building the BL31 image, we put the stub magic into the binary.
26 * The GPU firmware detects this at boot time, clears that field as a
27 * confirmation and puts the kernel and DT address in the following words.
28 */
29 extern uint32_t stub_magic;
30 extern uint32_t dtb_ptr32;
31 extern uint32_t kernel_entry32;
32
33 static const gicv2_driver_data_t rpi4_gic_data = {
34 .gicd_base = RPI4_GIC_GICD_BASE,
35 .gicc_base = RPI4_GIC_GICC_BASE,
36 };
37
38 /*
39 * To be filled by the code below. At the moment BL32 is not supported.
40 * In the future these might be passed down from BL2.
41 */
42 static entry_point_info_t bl32_image_ep_info;
43 static entry_point_info_t bl33_image_ep_info;
44
45 /*******************************************************************************
46 * Return a pointer to the 'entry_point_info' structure of the next image for
47 * the security state specified. BL33 corresponds to the non-secure image type
48 * while BL32 corresponds to the secure image type. A NULL pointer is returned
49 * if the image does not exist.
50 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)51 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
52 {
53 entry_point_info_t *next_image_info;
54
55 assert(sec_state_is_valid(type) != 0);
56
57 next_image_info = (type == NON_SECURE)
58 ? &bl33_image_ep_info : &bl32_image_ep_info;
59
60 /* None of the images can have 0x0 as the entrypoint. */
61 if (next_image_info->pc) {
62 return next_image_info;
63 } else {
64 return NULL;
65 }
66 }
67
plat_get_ns_image_entrypoint(void)68 uintptr_t plat_get_ns_image_entrypoint(void)
69 {
70 #ifdef PRELOADED_BL33_BASE
71 return PRELOADED_BL33_BASE;
72 #else
73 /* Cleared by the GPU if kernel address is valid. */
74 if (stub_magic == 0)
75 return kernel_entry32;
76
77 WARN("Stub magic failure, using default kernel address 0x80000\n");
78 return 0x80000;
79 #endif
80 }
81
rpi4_get_dtb_address(void)82 uintptr_t rpi4_get_dtb_address(void)
83 {
84 #ifdef RPI3_PRELOADED_DTB_BASE
85 return RPI3_PRELOADED_DTB_BASE;
86 #else
87 /* Cleared by the GPU if DTB address is valid. */
88 if (stub_magic == 0)
89 return dtb_ptr32;
90
91 WARN("Stub magic failure, DTB address unknown\n");
92 return 0;
93 #endif
94 }
95
ldelay(register_t delay)96 static void ldelay(register_t delay)
97 {
98 __asm__ volatile (
99 "1:\tcbz %0, 2f\n\t"
100 "sub %0, %0, #1\n\t"
101 "b 1b\n"
102 "2:"
103 : "=&r" (delay) : "0" (delay)
104 );
105 }
106
107 /*******************************************************************************
108 * Perform any BL31 early platform setup. Here is an opportunity to copy
109 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
110 * they are lost (potentially). This needs to be done before the MMU is
111 * initialized so that the memory layout can be used while creating page
112 * tables. BL2 has flushed this information to memory, so we are guaranteed
113 * to pick up good data.
114 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)115 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
116 u_register_t arg2, u_register_t arg3)
117
118 {
119 /*
120 * LOCAL_CONTROL:
121 * Bit 9 clear: Increment by 1 (vs. 2).
122 * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
123 */
124 mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
125
126 /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
127 mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
128
129 /* Early GPU firmware revisions need a little break here. */
130 ldelay(100000);
131
132 /* Initialize the console to provide early debug support. */
133 rpi3_console_init();
134
135 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
136 bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
137 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
138
139 #if RPI3_DIRECT_LINUX_BOOT
140 # if RPI3_BL33_IN_AARCH32
141 /*
142 * According to the file ``Documentation/arm/Booting`` of the Linux
143 * kernel tree, Linux expects:
144 * r0 = 0
145 * r1 = machine type number, optional in DT-only platforms (~0 if so)
146 * r2 = Physical address of the device tree blob
147 */
148 VERBOSE("rpi: Preparing to boot 32-bit Linux kernel\n");
149 bl33_image_ep_info.args.arg0 = 0U;
150 bl33_image_ep_info.args.arg1 = ~0U;
151 bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address();
152 # else
153 /*
154 * According to the file ``Documentation/arm64/booting.txt`` of the
155 * Linux kernel tree, Linux expects the physical address of the device
156 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
157 * must be 0.
158 */
159 VERBOSE("rpi: Preparing to boot 64-bit Linux kernel\n");
160 bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address();
161 bl33_image_ep_info.args.arg1 = 0ULL;
162 bl33_image_ep_info.args.arg2 = 0ULL;
163 bl33_image_ep_info.args.arg3 = 0ULL;
164 # endif /* RPI3_BL33_IN_AARCH32 */
165 #endif /* RPI3_DIRECT_LINUX_BOOT */
166 }
167
bl31_plat_arch_setup(void)168 void bl31_plat_arch_setup(void)
169 {
170 /*
171 * Is the dtb_ptr32 pointer valid? If yes, map the DTB region.
172 * We map the 2MB region the DTB start address lives in, plus
173 * the next 2MB, to have enough room for expansion.
174 */
175 if (stub_magic == 0) {
176 unsigned long long dtb_region = dtb_ptr32;
177
178 dtb_region &= ~0x1fffff; /* Align to 2 MB. */
179 mmap_add_region(dtb_region, dtb_region, 4U << 20,
180 MT_MEMORY | MT_RW | MT_NS);
181 }
182 /*
183 * Add the first page of memory, which holds the stub magic,
184 * the kernel and the DT address.
185 * This also holds the secondary CPU's entrypoints and mailboxes.
186 */
187 mmap_add_region(0, 0, 4096, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
188
189 rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
190 BL_CODE_BASE, BL_CODE_END,
191 BL_RO_DATA_BASE, BL_RO_DATA_END
192 #if USE_COHERENT_MEM
193 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
194 #endif
195 );
196
197 enable_mmu_el3(0);
198 }
199
bl31_platform_setup(void)200 void bl31_platform_setup(void)
201 {
202 /* Configure the interrupt controller */
203 gicv2_driver_init(&rpi4_gic_data);
204 gicv2_distif_init();
205 gicv2_pcpu_distif_init();
206 gicv2_cpuif_enable();
207
208 plat_rpi_bl31_custom_setup();
209 }
210