1 /*
2 * Copyright (c) 2021-2023, Stephan Gerhold <[email protected]>
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/bl_common.h>
8 #include <drivers/console.h>
9 #include <drivers/generic_delay_timer.h>
10 #include <lib/mmio.h>
11 #include <lib/xlat_tables/xlat_mmu_helpers.h>
12 #include <lib/xlat_tables/xlat_tables_v2.h>
13
14 #include "msm8916_gicv2.h"
15 #include <msm8916_mmap.h>
16 #include "msm8916_setup.h"
17 #include <uartdm_console.h>
18
19 static const mmap_region_t msm8916_mmap[] = {
20 MAP_REGION_FLAT(PCNOC_BASE, PCNOC_SIZE,
21 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
22 MAP_REGION_FLAT(APCS_BASE, APCS_SIZE,
23 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
24 {},
25 };
26
27 static console_t console;
28
plat_get_syscnt_freq2(void)29 unsigned int plat_get_syscnt_freq2(void)
30 {
31 return PLAT_SYSCNT_FREQ;
32 }
33
34 #define GPIO_CFG_FUNC(n) ((n) << 2)
35 #define GPIO_CFG_DRV_STRENGTH_MA(ma) (((ma) / 2 - 1) << 6)
36
37 #define CLK_ENABLE BIT_32(0)
38 #define CLK_OFF BIT_32(31)
39 #define GCC_BLSP1_AHB_CBCR (GCC_BASE + 0x01008)
40 #define GCC_BLSP1_UART_APPS_CBCR(n) (GCC_BASE + \
41 (((n) == 2) ? (0x0302c) : (0x0203c + (((n) - 1) * 0x1000))))
42 #define GCC_APCS_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x45004)
43 #define BLSP1_AHB_CLK_ENA BIT_32(10)
44
45 struct uartdm_gpios {
46 unsigned int tx, rx, func;
47 };
48
49 static const struct uartdm_gpios uartdm_gpio_map[] = {
50 #if defined(PLAT_msm8909)
51 {4, 5, 0x2}, {20, 21, 0x3},
52 #elif defined(PLAT_msm8916) || defined(PLAT_msm8939)
53 {0, 1, 0x2}, {4, 5, 0x2},
54 #elif defined(PLAT_mdm9607)
55 {12, 13, 0x2}, {4, 5, 0x2}, {0, 1, 0x1},
56 {16, 17, 0x2}, {8, 9, 0x2}, {20, 21, 0x2},
57 #endif
58 };
59
60 /*
61 * The previous boot stage seems to disable most of the UART setup before exit
62 * so it must be enabled here again before the UART console can be used.
63 */
msm8916_enable_blsp_uart(void)64 static void msm8916_enable_blsp_uart(void)
65 {
66 const struct uartdm_gpios *gpios = &uartdm_gpio_map[QTI_UART_NUM - 1];
67
68 CASSERT(QTI_UART_NUM > 0 && QTI_UART_NUM <= ARRAY_SIZE(uartdm_gpio_map),
69 assert_qti_blsp_uart_valid);
70
71 /* Route GPIOs to BLSP UART */
72 mmio_write_32(TLMM_GPIO_CFG(gpios->tx), GPIO_CFG_FUNC(gpios->func) |
73 GPIO_CFG_DRV_STRENGTH_MA(8));
74 mmio_write_32(TLMM_GPIO_CFG(gpios->rx), GPIO_CFG_FUNC(gpios->func) |
75 GPIO_CFG_DRV_STRENGTH_MA(8));
76
77 /* Enable AHB clock */
78 mmio_setbits_32(GCC_APCS_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA);
79 while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF) {
80 }
81
82 /* Enable BLSP UART clock */
83 mmio_setbits_32(GCC_BLSP1_UART_APPS_CBCR(QTI_UART_NUM), CLK_ENABLE);
84 while (mmio_read_32(GCC_BLSP1_UART_APPS_CBCR(QTI_UART_NUM)) & CLK_OFF) {
85 }
86 }
87
msm8916_early_platform_setup(void)88 void msm8916_early_platform_setup(void)
89 {
90 /* Initialize the debug console as early as possible */
91 msm8916_enable_blsp_uart();
92 console_uartdm_register(&console, BLSP_UART_BASE);
93
94 if (QTI_RUNTIME_UART) {
95 /* Mark UART as runtime usable */
96 console_set_scope(&console, CONSOLE_FLAG_BOOT |
97 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
98 }
99 }
100
msm8916_plat_arch_setup(uintptr_t base,size_t size)101 void msm8916_plat_arch_setup(uintptr_t base, size_t size)
102 {
103 mmap_add_region(base, base, size, MT_RW_DATA | MT_SECURE);
104 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
105 BL_CODE_END - BL_CODE_BASE,
106 MT_CODE | MT_SECURE);
107 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
108 BL_RO_DATA_END - BL_RO_DATA_BASE,
109 MT_RO_DATA | MT_SECURE);
110 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
111 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
112 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
113
114 mmap_add(msm8916_mmap);
115 init_xlat_tables();
116 }
117
msm8916_platform_setup(void)118 void msm8916_platform_setup(void)
119 {
120 generic_delay_timer_init();
121 msm8916_gicv2_init();
122 }
123