1 /*
2 * Author: Xianjun jiao, Michael Mehari, Wei Liu
3 * SPDX-FileCopyrightText: 2019 UGent
4 * SPDX-License-Identifier: AGPL-3.0-or-later
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/dmapool.h>
9 #include <linux/dma/xilinx_dma.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_dma.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_irq.h>
19 #include <linux/slab.h>
20 #include <linux/clk.h>
21 #include <linux/io-64-nonatomic-lo-hi.h>
22 #include <linux/delay.h>
23
24 #include "../hw_def.h"
25
26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
27
28 /* IO accessors */
reg_read(u32 reg)29 static inline u32 reg_read(u32 reg)
30 {
31 return ioread32(base_addr + reg);
32 }
33
reg_write(u32 reg,u32 value)34 static inline void reg_write(u32 reg, u32 value)
35 {
36 iowrite32(value, base_addr + reg);
37 }
38
OPENOFDM_RX_REG_STATE_HISTORY_read(void)39 static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){
40 return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR);
41 }
42
OPENOFDM_RX_REG_MULTI_RST_write(u32 Data)43 static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) {
44 reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data);
45 }
OPENOFDM_RX_REG_ENABLE_write(u32 Data)46 static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) {
47 reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data);
48 }
OPENOFDM_RX_REG_POWER_THRES_write(u32 Data)49 static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) {
50 reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data);
51 }
OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data)52 static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) {
53 reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data);
54 }
OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data)55 static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) {
56 reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data);
57 }
OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data)58 static inline void OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data) {
59 reg_write(OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR, Data);
60 }
61 static const struct of_device_id dev_of_ids[] = {
62 { .compatible = "sdr,openofdm_rx", },
63 {}
64 };
65 MODULE_DEVICE_TABLE(of, dev_of_ids);
66
67 static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst;
68 struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst;
69 EXPORT_SYMBOL(openofdm_rx_api);
70
hw_init(enum openofdm_rx_mode mode)71 static inline u32 hw_init(enum openofdm_rx_mode mode){
72 int err=0, i;
73
74 printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode);
75
76 switch(mode)
77 {
78 case OPENOFDM_RX_TEST:
79 {
80 printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str);
81 break;
82 }
83 case OPENOFDM_RX_NORMAL:
84 {
85 printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str);
86 break;
87 }
88 default:
89 {
90 printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode);
91 err=1;
92 }
93 }
94 printk("%s hw_init input: power_thres %d dc_running_sum_th %d min_plateau %d\n", openofdm_rx_compatible_str, OPENOFDM_RX_POWER_THRES_INIT, OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT, OPENOFDM_RX_MIN_PLATEAU_INIT);
95
96 // 1) power threshold configuration and reset
97 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default
98 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
99 openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold
100 openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT);
101
102 //rst
103 for (i=0;i<8;i++)
104 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
105 for (i=0;i<32;i++)
106 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
107 for (i=0;i<8;i++)
108 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
109
110 printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err);
111
112 return(err);
113 }
114
dev_probe(struct platform_device * pdev)115 static int dev_probe(struct platform_device *pdev)
116 {
117 struct device_node *np = pdev->dev.of_node;
118 struct resource *io;
119 int err=1;
120
121 printk("\n");
122
123 if (np) {
124 const struct of_device_id *match;
125
126 match = of_match_node(dev_of_ids, np);
127 if (match) {
128 printk("%s dev_probe match!\n", openofdm_rx_compatible_str);
129 err = 0;
130 }
131 }
132
133 if (err)
134 return err;
135
136 openofdm_rx_api->hw_init=hw_init;
137
138 openofdm_rx_api->reg_read=reg_read;
139 openofdm_rx_api->reg_write=reg_write;
140
141 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write;
142 openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write;
143 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write;
144 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write;
145 openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write;
146 openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write=OPENOFDM_RX_REG_FFT_WIN_SHIFT_write;
147
148 /* Request and map I/O memory */
149 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
150 base_addr = devm_ioremap_resource(&pdev->dev, io);
151 if (IS_ERR(base_addr))
152 return PTR_ERR(base_addr);
153
154 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
155 printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr);
156 printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);
157 printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api);
158
159 printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str);
160
161 err = hw_init(OPENOFDM_RX_NORMAL);
162
163 return err;
164 }
165
dev_remove(struct platform_device * pdev)166 static int dev_remove(struct platform_device *pdev)
167 {
168 printk("\n");
169
170 printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr);
171 printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);
172 printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api);
173
174 printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str);
175 return 0;
176 }
177
178 static struct platform_driver dev_driver = {
179 .driver = {
180 .name = "sdr,openofdm_rx",
181 .owner = THIS_MODULE,
182 .of_match_table = dev_of_ids,
183 },
184 .probe = dev_probe,
185 .remove = dev_remove,
186 };
187
188 module_platform_driver(dev_driver);
189
190 MODULE_AUTHOR("Xianjun Jiao");
191 MODULE_DESCRIPTION("sdr,openofdm_rx");
192 MODULE_LICENSE("GPL v2");
193